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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 | /* * Copyright (c) 2018, Cypress * * SPDX-License-Identifier: Apache-2.0 */ #include <device.h> #include <init.h> #include <arch/cpu.h> #include <cortex_m/exc.h> #include "cy_syslib.h" #include "cy_gpio.h" #include "cy_scb_uart.h" #include "cy_syslib.h" #include "cy_syspm.h" #include "cy_sysclk.h" #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 #define CY_CFG_SYSCLK_FLL_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL #define CY_CFG_SYSCLK_ILO_ENABLED 1 #define CY_CFG_SYSCLK_IMO_ENABLED 1 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 #define CY_CFG_PWR_ENABLED 1 #define CY_CFG_PWR_USING_LDO 1 #define CY_CFG_PWR_USING_PMIC 0 #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V #define CY_CFG_PWR_VDDA_MV 3300 #define CY_CFG_PWR_USING_ULP 0 static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = { .fllMult = 500u, .refDiv = 20u, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, .lockTolerance = 10u, .igain = 9u, .pgain = 5u, .settlingCount = 8u, .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO, .cco_Freq = 355u, }; static inline void Cy_SysClk_ClkFastInit(void) { Cy_SysClk_ClkFastSetDivider(0u); } static inline void Cy_SysClk_FllInit(void) { Cy_SysClk_FllManualConfigure(&srss_0__clock_0__fll_0__fllConfig); Cy_SysClk_FllEnable(200000u); } static inline void Cy_SysClk_ClkHf0Init(void) { Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0); Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE); Cy_SysClk_ClkHfEnable(0u); } static inline void Cy_SysClk_IloInit(void) { Cy_SysClk_IloEnable(); Cy_SysClk_IloHibernateOn(true); } static inline void Cy_SysClk_ClkLfInit(void) { Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO); } static inline void Cy_SysClk_ClkPath0Init(void) { Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO); } static inline void Cy_SysClk_ClkPath1Init(void) { Cy_SysClk_ClkPathSetSource(1u, CY_SYSCLK_CLKPATH_IN_IMO); } static inline void Cy_SysClk_ClkPath2Init(void) { Cy_SysClk_ClkPathSetSource(2u, CY_SYSCLK_CLKPATH_IN_IMO); } static inline void Cy_SysClk_ClkPath3Init(void) { Cy_SysClk_ClkPathSetSource(3u, CY_SYSCLK_CLKPATH_IN_IMO); } static inline void Cy_SysClk_ClkPath4Init(void) { Cy_SysClk_ClkPathSetSource(4u, CY_SYSCLK_CLKPATH_IN_IMO); } static inline void Cy_SysClk_ClkPeriInit(void) { Cy_SysClk_ClkPeriSetDivider(1u); } static inline void Cy_SysClk_ClkSlowInit(void) { Cy_SysClk_ClkSlowSetDivider(0u); } static void init_cycfg_platform(void) { /* Set worst case memory wait states (! ultra low power, 150 MHz), will * update at the end */ Cy_SysLib_SetWaitStates(false, 150); #ifdef CY_CFG_PWR_ENABLED /* Configure power mode */ #if CY_CFG_PWR_USING_LDO Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE); #else Cy_SysPm_BuckEnable(CY_CFG_PWR_SIMO_VOLTAGE); #endif /* Configure PMIC */ Cy_SysPm_UnlockPmic(); #if CY_CFG_PWR_USING_PMIC Cy_SysPm_PmicEnableOutput(); #else Cy_SysPm_PmicDisableOutput(); #endif #endif /* Enable all source clocks */ #ifdef CY_CFG_SYSCLK_PILO_ENABLED Cy_SysClk_PiloInit(); #endif #ifdef CY_CFG_SYSCLK_WCO_ENABLED Cy_SysClk_WcoInit(); #endif #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED Cy_SysClk_ClkLfInit(); #endif #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED Cy_SysClk_AltHfInit(); #endif #ifdef CY_CFG_SYSCLK_ECO_ENABLED Cy_SysClk_EcoInit(); #endif #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED Cy_SysClk_ExtClkInit(); #endif /* Configure CPU clock dividers */ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED Cy_SysClk_ClkFastInit(); #endif #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED Cy_SysClk_ClkPeriInit(); #endif #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED Cy_SysClk_ClkSlowInit(); #endif /* Configure HF clocks */ #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED Cy_SysClk_ClkHf0Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED Cy_SysClk_ClkHf1Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED Cy_SysClk_ClkHf2Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED Cy_SysClk_ClkHf3Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED Cy_SysClk_ClkHf4Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED Cy_SysClk_ClkHf5Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED Cy_SysClk_ClkHf6Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED Cy_SysClk_ClkHf7Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED Cy_SysClk_ClkHf8Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED Cy_SysClk_ClkHf9Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED Cy_SysClk_ClkHf10Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED Cy_SysClk_ClkHf11Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED Cy_SysClk_ClkHf12Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED Cy_SysClk_ClkHf13Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED Cy_SysClk_ClkHf14Init(); #endif #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED Cy_SysClk_ClkHf15Init(); #endif /* Configure Path Clocks */ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED Cy_SysClk_ClkPath0Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED Cy_SysClk_ClkPath1Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED Cy_SysClk_ClkPath2Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED Cy_SysClk_ClkPath3Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED Cy_SysClk_ClkPath4Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED Cy_SysClk_ClkPath5Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED Cy_SysClk_ClkPath6Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED Cy_SysClk_ClkPath7Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED Cy_SysClk_ClkPath8Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED Cy_SysClk_ClkPath9Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED Cy_SysClk_ClkPath10Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED Cy_SysClk_ClkPath11Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED Cy_SysClk_ClkPath12Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED Cy_SysClk_ClkPath13Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED Cy_SysClk_ClkPath14Init(); #endif #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED Cy_SysClk_ClkPath15Init(); #endif /* Configure and enable FLL */ #ifdef CY_CFG_SYSCLK_FLL_ENABLED Cy_SysClk_FllInit(); #endif /* Configure and enable PLLs */ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED Cy_SysClk_Pll0Init(); #endif #ifdef CY_CFG_SYSCLK_PLL1_ENABLED Cy_SysClk_Pll1Init(); #endif #ifdef CY_CFG_SYSCLK_PLL2_ENABLED Cy_SysClk_Pll2Init(); #endif #ifdef CY_CFG_SYSCLK_PLL3_ENABLED Cy_SysClk_Pll3Init(); #endif #ifdef CY_CFG_SYSCLK_PLL4_ENABLED Cy_SysClk_Pll4Init(); #endif #ifdef CY_CFG_SYSCLK_PLL5_ENABLED Cy_SysClk_Pll5Init(); #endif #ifdef CY_CFG_SYSCLK_PLL6_ENABLED Cy_SysClk_Pll6Init(); #endif #ifdef CY_CFG_SYSCLK_PLL7_ENABLED Cy_SysClk_Pll7Init(); #endif #ifdef CY_CFG_SYSCLK_PLL8_ENABLED Cy_SysClk_Pll8Init(); #endif #ifdef CY_CFG_SYSCLK_PLL9_ENABLED Cy_SysClk_Pll9Init(); #endif #ifdef CY_CFG_SYSCLK_PLL10_ENABLED Cy_SysClk_Pll10Init(); #endif #ifdef CY_CFG_SYSCLK_PLL11_ENABLED Cy_SysClk_Pll11Init(); #endif #ifdef CY_CFG_SYSCLK_PLL12_ENABLED Cy_SysClk_Pll12Init(); #endif #ifdef CY_CFG_SYSCLK_PLL13_ENABLED Cy_SysClk_Pll13Init(); #endif #ifdef CY_CFG_SYSCLK_PLL14_ENABLED Cy_SysClk_Pll14Init(); #endif /* Configure miscellaneous clocks */ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED Cy_SysClk_ClkTimerInit(); #endif #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED Cy_SysClk_ClkAltSysTickInit(); #endif #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED Cy_SysClk_ClkPumpInit(); #endif #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED Cy_SysClk_ClkBakInit(); #endif /* Configure default enabled clocks */ #ifdef CY_CFG_SYSCLK_ILO_ENABLED Cy_SysClk_IloInit(); #else Cy_SysClk_IloDisable(); #endif #ifndef CY_CFG_SYSCLK_IMO_ENABLED #error the IMO must be enabled for proper chip operation #endif /* Set accurate flash wait states */ #if (defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_SYSCLK_CLKHF0_ENABLED)) Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); #endif } /** * Function Name: Cy_SystemInit * * \brief This function is called by the start-up code for the selected device. * It performs all of the necessary device configuration based on the design * settings. This includes settings for the platform resources and peripheral * clock. * */ void Cy_SystemInit(void) { /* Configure platform resources */ init_cycfg_platform(); /* Configure peripheral clocks */ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u); } static int init_cycfg_platform_wraper(struct device *arg) { ARG_UNUSED(arg); SystemInit(); return 0; } SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0); |