Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 | /* * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com> * Contributors: 2018 Antmicro <www.antmicro.com> * * SPDX-License-Identifier: Apache-2.0 */ /** * @brief Platform Level Interrupt Controller (PLIC) driver * for RISC-V processors */ #include <kernel.h> #include <arch/cpu.h> #include <init.h> #include "plic.h" #include <sw_isr_table.h> struct plic_regs_t { u32_t threshold_prio; u32_t claim_complete; }; static int save_irq; /** * * @brief Enable a riscv PLIC-specific interrupt line * * This routine enables a RISCV PLIC-specific interrupt line. * riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGE * z_arch_irq_enable function to enable external interrupts for * IRQS > RISCV_MAX_GENERIC_IRQ, whenever CONFIG_RISCV_HAS_PLIC * variable is set. * @param irq IRQ number to enable * * @return N/A */ void riscv_plic_irq_enable(u32_t irq) { u32_t key; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; volatile u32_t *en = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS; key = irq_lock(); en += (plic_irq >> 5); *en |= (1 << (plic_irq & 31)); irq_unlock(key); } /** * * @brief Disable a riscv PLIC-specific interrupt line * * This routine disables a RISCV PLIC-specific interrupt line. * riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGE * z_arch_irq_disable function to disable external interrupts, for * IRQS > RISCV_MAX_GENERIC_IRQ, whenever CONFIG_RISCV_HAS_PLIC * variable is set. * @param irq IRQ number to disable * * @return N/A */ void riscv_plic_irq_disable(u32_t irq) { u32_t key; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; volatile u32_t *en = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS; key = irq_lock(); en += (plic_irq >> 5); *en &= ~(1 << (plic_irq & 31)); irq_unlock(key); } /** * * @brief Check if a riscv PLIC-specific interrupt line is enabled * * This routine checks if a RISCV PLIC-specific interrupt line is enabled. * @param irq IRQ number to check * * @return 1 or 0 */ int riscv_plic_irq_is_enabled(u32_t irq) { volatile u32_t *en = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS; u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ; en += (plic_irq >> 5); return !!(*en & (1 << (plic_irq & 31))); } /** * * @brief Set priority of a riscv PLIC-specific interrupt line * * This routine set the priority of a RISCV PLIC-specific interrupt line. * riscv_plic_irq_set_prio is called by riscv Z_ARCH_IRQ_CONNECT to set * the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set. * @param irq IRQ number for which to set priority * * @return N/A */ void riscv_plic_set_priority(u32_t irq, u32_t priority) { volatile u32_t *prio = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS; /* Can set priority only for PLIC-specific interrupt line */ if (irq <= RISCV_MAX_GENERIC_IRQ) return; if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY) priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY; prio += (irq - RISCV_MAX_GENERIC_IRQ); *prio = priority; } /** * * @brief Get riscv PLIC-specific interrupt line causing an interrupt * * This routine returns the RISCV PLIC-specific interrupt line causing an * interrupt. * @param irq IRQ number for which to set priority * * @return N/A */ int riscv_plic_get_irq(void) { return save_irq; } static void plic_irq_handler(void *arg) { volatile struct plic_regs_t *regs = (volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS; u32_t irq; struct _isr_table_entry *ite; /* Get the IRQ number generating the interrupt */ irq = regs->claim_complete; /* * Save IRQ in save_irq. To be used, if need be, by * subsequent handlers registered in the _sw_isr_table table, * as IRQ number held by the claim_complete register is * cleared upon read. */ save_irq = irq; /* * If the IRQ is out of range, call z_irq_spurious. * A call to z_irq_spurious will not return. */ if (irq == 0U || irq >= PLIC_IRQS) z_irq_spurious(NULL); irq += RISCV_MAX_GENERIC_IRQ; /* Call the corresponding IRQ handler in _sw_isr_table */ ite = (struct _isr_table_entry *)&_sw_isr_table[irq]; ite->isr(ite->arg); /* * Write to claim_complete register to indicate to * PLIC controller that the IRQ has been handled. */ regs->claim_complete = save_irq; } /** * * @brief Initialize the Platform Level Interrupt Controller * @return N/A */ static int plic_init(struct device *dev) { ARG_UNUSED(dev); volatile u32_t *en = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS; volatile u32_t *prio = (volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS; volatile struct plic_regs_t *regs = (volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS; int i; /* Ensure that all interrupts are disabled initially */ for (i = 0; i < PLIC_EN_SIZE; i++) { *en = 0U; en++; } /* Set priority of each interrupt line to 0 initially */ for (i = 0; i < PLIC_IRQS; i++) { *prio = 0U; prio++; } /* Set threshold priority to 0 */ regs->threshold_prio = 0U; /* Setup IRQ handler for PLIC driver */ IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ, 0, plic_irq_handler, NULL, 0); /* Enable IRQ for PLIC driver */ irq_enable(RISCV_MACHINE_EXT_IRQ); return 0; } SYS_INIT(plic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); |