Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 | /* * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_msmc.h" #if defined(__riscv) #define CONFIG_NORMAL_SLEEP EVENT_UNIT->SLPCTRL = (EVENT_UNIT->SLPCTRL & ~0x03) | (1 << 0) #define CONFIG_DEEP_SLEEP EVENT_UNIT->SLPCTRL |= 0x03; #else #define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk #define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk #endif status_t SMC_SetPowerModeRun(SMC_Type *base) { uint32_t reg; reg = base->PMCTRL; /* configure Normal RUN mode */ reg &= ~SMC_PMCTRL_RUNM_MASK; reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); base->PMCTRL = reg; return kStatus_Success; } status_t SMC_SetPowerModeHsrun(SMC_Type *base) { uint32_t reg; reg = base->PMCTRL; /* configure High Speed RUN mode */ reg &= ~SMC_PMCTRL_RUNM_MASK; reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); base->PMCTRL = reg; return kStatus_Success; } status_t SMC_SetPowerModeWait(SMC_Type *base) { /* configure Normal Wait mode */ CONFIG_NORMAL_SLEEP; __DSB(); __WFI(); __ISB(); return kStatus_Success; } status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) { uint32_t reg; /* configure the Partial Stop mode in Noraml Stop mode */ reg = base->PMCTRL; reg &= ~(SMC_PMCTRL_PSTOPO_MASK | SMC_PMCTRL_STOPM_MASK); reg |= ((uint32_t)option << SMC_PMCTRL_PSTOPO_SHIFT) | (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ CONFIG_DEEP_SLEEP; /* read back to make sure the configuration valid before entering stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); #if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) /* check whether the power mode enter Stop mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) { return kStatus_SMC_StopAbort; } else { return kStatus_Success; } #else return kStatus_Success; #endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ } status_t SMC_SetPowerModeVlpr(SMC_Type *base) { uint32_t reg; reg = base->PMCTRL; /* configure VLPR mode */ reg &= ~SMC_PMCTRL_RUNM_MASK; reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); base->PMCTRL = reg; return kStatus_Success; } status_t SMC_SetPowerModeVlpw(SMC_Type *base) { /* configure VLPW mode */ /* Clear the SLEEPDEEP bit to disable deep sleep mode */ CONFIG_NORMAL_SLEEP; __DSB(); __WFI(); __ISB(); return kStatus_Success; } status_t SMC_SetPowerModeVlps(SMC_Type *base) { uint32_t reg; /* configure VLPS mode */ reg = base->PMCTRL; reg &= ~SMC_PMCTRL_STOPM_MASK; reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; /* Set the SLEEPDEEP bit to enable deep sleep mode */ CONFIG_DEEP_SLEEP; /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); #if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) /* check whether the power mode enter Stop mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) { return kStatus_SMC_StopAbort; } else { return kStatus_Success; } #else return kStatus_Success; #endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ } status_t SMC_SetPowerModeLls(SMC_Type *base) { uint32_t reg; /* configure to LLS mode */ reg = base->PMCTRL; reg &= ~SMC_PMCTRL_STOPM_MASK; reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; /* Set the SLEEPDEEP bit to enable deep sleep mode */ CONFIG_DEEP_SLEEP; /* read back to make sure the configuration valid before entering stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); #if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) /* check whether the power mode enter Stop mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) { return kStatus_SMC_StopAbort; } else { return kStatus_Success; } #else return kStatus_Success; #endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ } #if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) status_t SMC_SetPowerModeVlls0(SMC_Type *base) { uint32_t reg; /* configure to VLLS mode */ reg = base->PMCTRL; reg &= ~SMC_PMCTRL_STOPM_MASK; reg |= (kSMC_StopVlls0 << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; /* Set the SLEEPDEEP bit to enable deep sleep mode */ CONFIG_DEEP_SLEEP; /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); return kStatus_Success; } #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ #if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) status_t SMC_SetPowerModeVlls2(SMC_Type *base) { uint32_t reg; /* configure to VLLS mode */ reg = base->PMCTRL; reg &= ~SMC_PMCTRL_STOPM_MASK; reg |= (kSMC_StopVlls2 << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; /* Set the SLEEPDEEP bit to enable deep sleep mode */ CONFIG_DEEP_SLEEP; /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); return kStatus_Success; } #endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */ #else /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ status_t SMC_SetPowerModeVlls(SMC_Type *base) { uint32_t reg; /* configure to VLLS mode */ reg = base->PMCTRL; reg &= ~SMC_PMCTRL_STOPM_MASK; reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); base->PMCTRL = reg; #if defined(__riscv) EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1); #else /* Set the SLEEPDEEP bit to enable deep sleep mode */ CONFIG_DEEP_SLEEP; #endif /* read back to make sure the configuration valid before enter stop mode */ (void)base->PMCTRL; __DSB(); __WFI(); __ISB(); #if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) /* check whether the power mode enter Stop mode succeed */ if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) { return kStatus_SMC_StopAbort; } else { return kStatus_Success; } #else return kStatus_Success; #endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */ } #endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */ void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config) { assert(config); uint32_t reg; reg = SMC_RPC_FILTCFG(config->slowClockFilterCount) | SMC_RPC_FILTEN(config->enableFilter); #if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN) if (config->enableLpoFilter) { reg |= SMC_RPC_LPOFEN_MASK; } #endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */ base->RPC = reg; } |