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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 | /* * Copyright 2013-2016 Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause * */ #include "fsl_ftfx_cache.h" /******************************************************************************* * Definitions ******************************************************************************/ /*! * @name Flash cache and speculation control defines * @{ */ #if defined(MCM_PLACR_CFCC_MASK) #define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) #else #define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) #endif #define FLASH_CACHE_IS_CONTROLLED_BY_MSCM (0) #if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) #define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) #else #define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) #endif #if defined(MCM_PLACR_DFCS_MASK) #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) #else #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) #endif #if defined(MSCM_OCMDR_OCMC1_MASK) || defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR0_OCM1_MASK) || \ defined(MSCM_OCMDR1_OCM1_MASK) #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) #else #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) #endif #if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \ defined(FMC_PFB01CR_S_B_INV_MASK) #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) #else #define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) #endif #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC || \ FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_FMC || FLASH_CACHE_IS_CONTROLLED_BY_MSCM #define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (1) #else #define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (0) #endif /*@}*/ /*! @brief A function pointer used to point to relocated ftfx_common_bit_operation() */ typedef void (*callftfxCommonBitOperation_t)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t bitValue); /******************************************************************************* * Prototypes ******************************************************************************/ #if FLASH_CACHE_IS_CONTROLLED_BY_MCM /*! @brief Performs the cache clear to the flash by MCM.*/ void mcm_flash_cache_clear(ftfx_cache_config_t *config); #endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ #if FLASH_CACHE_IS_CONTROLLED_BY_MSCM /*! @brief Performs the cache clear to the flash by MSCM.*/ void mscm_flash_cache_clear(ftfx_cache_config_t *config); #endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */ #if FLASH_CACHE_IS_CONTROLLED_BY_FMC /*! @brief Performs the cache clear to the flash by FMC.*/ void fmc_flash_cache_clear(ftfx_cache_config_t *config); #endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM /*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable); #endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC /*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config); #endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ #if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE /*! @brief Copy flash_cache_clear_command() to RAM*/ static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation); #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ /******************************************************************************* * Variables ******************************************************************************/ #if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE /*! * @brief Position independent code of ftfx_common_bit_operation() * * Note1: The prototype of C function is shown as below: * @code * void ftfx_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t * bitValue) * { * if (bitMask) * { * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); * *base = (*base & (~bitMask)) | value; * } * * __ISB(); * __DSB(); * } * @endcode * Note2: The binary code is generated by IAR 7.70.1 */ static const uint16_t s_ftfxCommonBitOperationFunctionCode[] = { 0xb510, /* PUSH {R4, LR} */ 0x2900, /* CMP R1, #0 */ 0xd005, /* BEQ.N @12 */ 0x6804, /* LDR R4, [R0] */ 0x438c, /* BICS R4, R4, R1 */ 0x4093, /* LSLS R3, R3, R2 */ 0x4019, /* ANDS R1, R1, R3 */ 0x4321, /* ORRS R1, R1, R4 */ 0x6001, /* STR R1, [R0] */ /* @12: */ 0xf3bf, 0x8f6f, /* ISB */ 0xf3bf, 0x8f4f, /* DSB */ 0xbd10 /* POP {R4, PC} */ }; #if (!FTFx_DRIVER_IS_EXPORTED) /*! @brief A static buffer used to hold ftfx_common_bit_operation() */ static uint32_t s_ftfxCommonBitOperation[kFTFx_CACHE_RamFuncMaxSizeInWords]; #endif /* (!FTFx_DRIVER_IS_EXPORTED) */ #endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */ /******************************************************************************* * Code ******************************************************************************/ status_t FTFx_CACHE_Init(ftfx_cache_config_t *config) { if (config == NULL) { return kStatus_FTFx_InvalidArgument; } /* copy required flash commands to RAM */ #if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE if (NULL == config->comBitOperFuncAddr) { #if FTFx_DRIVER_IS_EXPORTED return kStatus_FTFx_ExecuteInRamFunctionNotReady; #else config->comBitOperFuncAddr = s_ftfxCommonBitOperation; #endif /* FTFx_DRIVER_IS_EXPORTED */ } ftfx_copy_common_bit_operation_to_ram(config->comBitOperFuncAddr); #endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */ return kStatus_FTFx_Success; } /*! * @brief Flash Cache/Prefetch/Speculation Clear Process * * This function is used to perform the cache and prefetch speculation clear process to the flash. */ status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess) { /* We pass the ftfx register address as a parameter to ftfx_common_bit_operation() instead of using * pre-processed MACROs or a global variable in ftfx_common_bit_operation() * to make sure that ftfx_common_bit_operation() will be compiled into position-independent code (PIC). */ if (!isPreProcess) { #if FLASH_CACHE_IS_CONTROLLED_BY_MCM mcm_flash_cache_clear(config); #endif #if FLASH_CACHE_IS_CONTROLLED_BY_MSCM mscm_flash_cache_clear(config); #endif #if FLASH_CACHE_IS_CONTROLLED_BY_FMC fmc_flash_cache_clear(config); #endif #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM mscm_flash_prefetch_speculation_enable(config, true); #endif #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC fmc_flash_prefetch_speculation_clear(config); #endif } if (isPreProcess) { #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM mscm_flash_prefetch_speculation_enable(config, false); #endif } return kStatus_FTFx_Success; } status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus) { #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM { if (speculationStatus->instructionOff) { if (!speculationStatus->dataOff) { return kStatus_FTFx_InvalidSpeculationOption; } else { MCM0_CACHE_REG |= MCM_PLACR_DFCS_MASK; } } else { MCM0_CACHE_REG &= ~MCM_PLACR_DFCS_MASK; if (!speculationStatus->dataOff) { MCM0_CACHE_REG |= MCM_PLACR_EFDS_MASK; } else { MCM0_CACHE_REG &= ~MCM_PLACR_EFDS_MASK; } } } #elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC { if (!speculationStatus->instructionOff) { FMC_CACHE_REG |= FMC_CACHE_B0IPE_MASK; } else { FMC_CACHE_REG &= ~FMC_CACHE_B0IPE_MASK; } if (!speculationStatus->dataOff) { FMC_CACHE_REG |= FMC_CACHE_B0DPE_MASK; } else { FMC_CACHE_REG &= ~FMC_CACHE_B0DPE_MASK; } /* Invalidate Prefetch Speculation Buffer */ FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK; } #elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM { if (speculationStatus->instructionOff) { if (!speculationStatus->dataOff) { return kStatus_FTFx_InvalidSpeculationOption; } else { MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFCS_MASK; } } else { MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFCS_MASK; if (!speculationStatus->dataOff) { MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFDS_MASK; } else { MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFDS_MASK; } } } #endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ return kStatus_FTFx_Success; } status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus) { memset(speculationStatus, 0, sizeof(ftfx_prefetch_speculation_status_t)); /* Assuming that all speculation options are enabled. */ speculationStatus->instructionOff = false; speculationStatus->dataOff = false; #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM { uint32_t value = MCM0_CACHE_REG; if (value & MCM_PLACR_DFCS_MASK) { /* Speculation buffer is off. */ speculationStatus->instructionOff = true; speculationStatus->dataOff = true; } else { /* Speculation buffer is on for instruction. */ if (!(value & MCM_PLACR_EFDS_MASK)) { /* Speculation buffer is off for data. */ speculationStatus->dataOff = true; } } } #elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC { uint32_t value = FMC_CACHE_REG; if (!(value & FMC_CACHE_B0DPE_MASK)) { /* Do not prefetch in response to data references. */ speculationStatus->dataOff = true; } if (!(value & FMC_CACHE_B0IPE_MASK)) { /* Do not prefetch in response to instruction fetches. */ speculationStatus->instructionOff = true; } } #elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM { uint32_t value = MSCM_OCMDR0_REG; if (value & MSCM_OCMDR_OCMC1_DFCS_MASK) { /* Speculation buffer is off. */ speculationStatus->instructionOff = true; speculationStatus->dataOff = true; } else { /* Speculation buffer is on for instruction. */ if (value & MSCM_OCMDR_OCMC1_DFDS_MASK) { /* Speculation buffer is off for data. */ speculationStatus->dataOff = true; } } } #endif return kStatus_FTFx_Success; } #if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE /*! @brief Copy PIC of ftfx_common_bit_operation() to RAM */ static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation) { assert(sizeof(s_ftfxCommonBitOperationFunctionCode) <= (kFTFx_CACHE_RamFuncMaxSizeInWords * 4)); memcpy(ftfxCommonBitOperation, s_ftfxCommonBitOperationFunctionCode, sizeof(s_ftfxCommonBitOperationFunctionCode)); } #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE */ #if FLASH_CACHE_IS_CONTROLLED_BY_MCM /*! @brief Performs the cache clear to the flash by MCM.*/ void mcm_flash_cache_clear(ftfx_cache_config_t *config) { FTFx_REG32_ACCESS_TYPE regBase; #if defined(MCM0_CACHE_REG) regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; #elif defined(MCM1_CACHE_REG) regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; #endif #if FTFx_DRIVER_IS_FLASH_RESIDENT /* Since the value of ARM function pointer is always odd, but the real start address * of function memory should be even, that's why +1 operation exist. */ callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); callftfxCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); #else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ *regBase |= MCM_CACHE_CLEAR_MASK; /* Memory barriers for good measure. * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ __ISB(); __DSB(); #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ } #endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ #if FLASH_CACHE_IS_CONTROLLED_BY_MSCM /*! @brief Performs the cache clear to the flash by MSCM.*/ void mscm_flash_cache_clear(ftfx_cache_config_t *config) { uint8_t setValue = 0x1U; /* The OCMDR[0] is always used to cache main Pflash*/ /* For device with FlexNVM support, the OCMDR[1] is used to cache Dflash. * For device with secondary flash support, the OCMDR[1] is used to cache secondary Pflash. */ #if FTFx_DRIVER_IS_FLASH_RESIDENT /* Since the value of ARM function pointer is always odd, but the real start address * of function memory should be even, that's why +1 operation exist. */ callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); switch (config->flashMemoryIndex) { case kFLASH_MemoryIndexSecondaryFlash: callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_CACHE_CLEAR_MASK, MSCM_CACHE_CLEAR_SHIFT, setValue); break; case kFLASH_MemoryIndexPrimaryFlash: default: callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_CACHE_CLEAR_MASK, MSCM_CACHE_CLEAR_SHIFT, setValue); break; } #else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ switch (config->flashMemoryIndex) { case kFLASH_MemoryIndexSecondaryFlash: MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue); /* Each cache clear instruction should be followed by below code*/ __ISB(); __DSB(); break; case kFLASH_MemoryIndexPrimaryFlash: default: MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue); /* Memory barriers for good measure. * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ __ISB(); __DSB(); break; } #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ } #endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */ #if FLASH_CACHE_IS_CONTROLLED_BY_FMC /*! @brief Performs the cache clear to the flash by FMC.*/ void fmc_flash_cache_clear(ftfx_cache_config_t *config) { #if FTFx_DRIVER_IS_FLASH_RESIDENT /* Since the value of ARM function pointer is always odd, but the real start address * of function memory should be even, that's why +1 operation exist. */ callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_CACHE_REG, FMC_CACHE_CLEAR_MASK, FMC_CACHE_CLEAR_SHIFT, 0xFU); #else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ FMC_CACHE_REG = (FMC_CACHE_REG & (~FMC_CACHE_CLEAR_MASK)) | FMC_CACHE_CLEAR(~0); /* Memory barriers for good measure. * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ __ISB(); __DSB(); #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ } #endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM /*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable) { uint8_t setValue; if (enable) { setValue = 0x0U; } else { setValue = 0x3U; } /* The OCMDR[0] is always used to prefetch main Pflash*/ /* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ #if FTFx_DRIVER_IS_FLASH_RESIDENT /* Since the value of ARM function pointer is always odd, but the real start address * of function memory should be even, that's why +1 operation exist. */ callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); switch (config->flashMemoryIndex) { case 1: callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_SPECULATION_SET_MASK, MSCM_SPECULATION_SET_SHIFT, setValue); break; case 0: default: callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_SPECULATION_SET_MASK, MSCM_SPECULATION_SET_SHIFT, setValue); break; } #else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ switch (config->flashMemoryIndex) { case kFLASH_MemoryIndexSecondaryFlash: MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue); /* Each cache clear instruction should be followed by below code*/ __ISB(); __DSB(); break; case kFLASH_MemoryIndexPrimaryFlash: default: MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue); /* Memory barriers for good measure. * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ __ISB(); __DSB(); break; } #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ } #endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ #if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC /*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config) { #if FTFx_DRIVER_IS_FLASH_RESIDENT /* Since the value of ARM function pointer is always odd, but the real start address * of function memory should be even, that's why +1 operation exist. */ callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1); callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_SPECULATION_INVALIDATE_REG, FMC_SPECULATION_INVALIDATE_MASK, FMC_SPECULATION_INVALIDATE_SHIFT, 1U); #else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */ FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK; /* Memory barriers for good measure. * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ __ISB(); __DSB(); #endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */ } #endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ |