Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 | /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2018 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_flexcan.h" /******************************************************************************* * Definitions ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.flexcan" #endif #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) /*! @name DBG1 - Debug 1 register */ #if !(defined(CAN_DBG1_CFSM_MASK) && defined(CAN_DBG1_CBN_MASK)) #define CAN_DBG1_CFSM_MASK (0x7FU) #define CAN_DBG1_CFSM_SHIFT (0U) #define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) #define CAN_DBG1_CBN_MASK (0x3FF0000U) #define CAN_DBG1_CBN_SHIFT (16U) #define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) #endif #define OFFSET_DBG1 (0x58U) #define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) #define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) #define BUSIDLE (CAN_DBG1_CFSM(0x02)) #define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) #define DELAY_BUSIDLE (200) #endif /*! @brief FlexCAN Internal State. */ enum _flexcan_state { kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ }; /*! @brief FlexCAN message buffer CODE for Rx buffers. */ enum _flexcan_mb_code_rx { kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ /*! The CPU must not access the MB.*/ kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ /*! and transmit a Response Frame in return.*/ kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ }; /*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ enum _flexcan_mb_code_tx { kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ /*! an incoming Remote Request Frame.*/ kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ }; /* Typedef for interrupt handler. */ typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); /******************************************************************************* * Prototypes ******************************************************************************/ /*! * @brief Enter FlexCAN Freeze Mode. * * This function makes the FlexCAN work under Freeze Mode. * * @param base FlexCAN peripheral base address. */ static void FLEXCAN_EnterFreezeMode(CAN_Type *base); /*! * @brief Exit FlexCAN Freeze Mode. * * This function makes the FlexCAN leave Freeze Mode. * * @param base FlexCAN peripheral base address. */ static void FLEXCAN_ExitFreezeMode(CAN_Type *base); #if !defined(NDEBUG) /*! * @brief Check if Message Buffer is occupied by Rx FIFO. * * This function check if Message Buffer is occupied by Rx FIFO. * * @param base FlexCAN peripheral base address. * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); #endif #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) /*! * @brief Get the first valid Message buffer ID of give FlexCAN instance. * * This function is a helper function for Errata 5641 workaround. * * @param base FlexCAN peripheral base address. * @return The first valid Message Buffer Number. */ static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); #endif /*! * @brief Check if Message Buffer interrupt is enabled. * * This function check if Message Buffer interrupt is enabled. * * @param base FlexCAN peripheral base address. * @param mbIdx The FlexCAN Message Buffer index. */ static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); /*! * @brief Reset the FlexCAN Instance. * * Restores the FlexCAN module to reset state, notice that this function * will set all the registers to reset state so the FlexCAN module can not work * after calling this API. * * @param base FlexCAN peripheral base address. */ static void FLEXCAN_Reset(CAN_Type *base); /*! * @brief Set Baud Rate of FlexCAN. * * This function set the baud rate of FlexCAN. * * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRate_Bps Baud Rate in Bps. * @param timingConfig FlexCAN timingConfig. */ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps, flexcan_timing_config_t timingConfig); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * @brief Set Baud Rate of FlexCAN FD frame. * * This function set the baud rate of FlexCAN FD frame. * * @param base FlexCAN peripheral base address. * @param sourceClock_Hz Source Clock in Hz. * @param baudRateFD_Bps FD frame Baud Rate in Bps. * @param timingConfig FlexCAN timingConfig. */ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig); /*! * @brief Get Mailbox offset number by dword. * * This function gets the offset number of the specified mailbox. * Mailbox is not consecutive between memory regions when payload is not 8 bytes * so need to calculate the specified mailbox address. * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. * * @param base FlexCAN peripheral base address. * @param mbIdx Mailbox index. */ static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); #endif /******************************************************************************* * Variables ******************************************************************************/ /* Array of FlexCAN peripheral base address. */ static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; /* Array of FlexCAN IRQ number. */ static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; /* Array of FlexCAN handle. */ static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Array of FlexCAN clock name. */ static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; #if defined(FLEXCAN_PERIPH_CLOCKS) /* Array of FlexCAN serial clock name. */ static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* FlexCAN ISR for transactional APIs. */ static flexcan_isr_t s_flexcanIsr; /******************************************************************************* * Code ******************************************************************************/ /*! * brief Get the FlexCAN instance from peripheral base address. * * param base FlexCAN peripheral base address. * return FlexCAN instance. */ uint32_t FLEXCAN_GetInstance(CAN_Type *base) { uint32_t instance; /* Find the instance index from base address mappings. */ for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) { if (s_flexcanBases[instance] == base) { break; } } assert(instance < ARRAY_SIZE(s_flexcanBases)); return instance; } static void FLEXCAN_EnterFreezeMode(CAN_Type *base) { #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) uint32_t u32TempMCR = 0U; uint32_t u32TimeoutCount = 0U; #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) uint32_t u32TempIMASK2 = 0U; #endif uint32_t u32TempIMASK1 = 0U; #endif /* Set Freeze, Halt bits. */ base->MCR |= CAN_MCR_FRZ_MASK; base->MCR |= CAN_MCR_HALT_MASK; /* Wait until the FlexCAN Module enter freeze mode. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; do { u32TempMCR = base->MCR; u32TimeoutCount--; } while ((!(u32TempMCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0)); if (!(u32TempMCR & CAN_MCR_FRZACK_MASK)) { /* Backup IMASK register */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) u32TempIMASK2 = base->IMASK2; #endif u32TempIMASK1 = base->IMASK1; base->MCR |= CAN_MCR_SOFTRST_MASK; /* Wait until until the Soft Reset (SOFTRST in MCR) bit is cleared */ u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; do { u32TempMCR = base->MCR; u32TimeoutCount--; } while ((!(u32TempMCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0)); /* Reconfigure the MCR and all Interrupt Mask Registers (IMASKn) */ base->MCR = u32TempMCR; #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) base->IMASK2 = u32TempIMASK2; #endif base->IMASK1 = u32TempIMASK1; } #else while (!(base->MCR & CAN_MCR_FRZACK_MASK)) { } #endif } static void FLEXCAN_ExitFreezeMode(CAN_Type *base) { /* Clear Freeze, Halt bits. */ base->MCR &= ~CAN_MCR_HALT_MASK; base->MCR &= ~CAN_MCR_FRZ_MASK; /* Wait until the FlexCAN Module exit freeze mode. */ while (base->MCR & CAN_MCR_FRZACK_MASK) { } } #if !defined(NDEBUG) static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) { uint8_t lastOccupiedMb; /* Is Rx FIFO enabled? */ if (base->MCR & CAN_MCR_RFEN_MASK) { /* Get RFFN value. */ lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (mbIdx <= (lastOccupiedMb + 1)) #else if (mbIdx <= lastOccupiedMb) #endif { return true; } else { return false; } } else { #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) if (0 == mbIdx) { return true; } else { return false; } #else return false; #endif } } #endif #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) { uint32_t firstValidMbNum; if (base->MCR & CAN_MCR_RFEN_MASK) { firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; } else { firstValidMbNum = 0; } return firstValidMbNum; } #endif static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) { /* Assertion. */ assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); #if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) if (mbIdx < 32) { #endif if (base->IMASK1 & ((uint32_t)(1 << mbIdx))) { return true; } else { return false; } #if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) } else { if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32)))) { return true; } else { return false; } } #endif } static void FLEXCAN_Reset(CAN_Type *base) { /* The module must should be first exit from low power * mode, and then soft reset can be applied. */ assert(!(base->MCR & CAN_MCR_MDIS_MASK)); uint8_t i; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) { /* De-assert DOZE Enable Bit. */ base->MCR &= ~CAN_MCR_DOZE_MASK; } #endif /* Wait until FlexCAN exit from any Low Power Mode. */ while (base->MCR & CAN_MCR_LPMACK_MASK) { } /* Assert Soft Reset Signal. */ base->MCR |= CAN_MCR_SOFTRST_MASK; /* Wait until FlexCAN reset completes. */ while (base->MCR & CAN_MCR_SOFTRST_MASK) { } /* Reset MCR register. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #else base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); #endif /* Reset CTRL1 and CTRL2 register. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /* SMP bit cannot be asserted when CAN FD is enabled */ if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) { base->CTRL1 = 0x0; } else { base->CTRL1 = CAN_CTRL1_SMP_MASK; } #else base->CTRL1 = CAN_CTRL1_SMP_MASK; #endif base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; /* Clean all individual Rx Mask of Message Buffers. */ for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) { base->RXIMR[i] = 0x3FFFFFFF; } /* Clean Global Mask of Message Buffers. */ base->RXMGMASK = 0x3FFFFFFF; /* Clean Global Mask of Message Buffer 14. */ base->RX14MASK = 0x3FFFFFFF; /* Clean Global Mask of Message Buffer 15. */ base->RX15MASK = 0x3FFFFFFF; /* Clean Global Mask of Rx FIFO. */ base->RXFGMASK = 0x3FFFFFFF; /* Clean all Message Buffer CS fields. */ for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) { base->MB[i].CS = 0x0; } } static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps, flexcan_timing_config_t timingConfig) { /* FlexCAN timing setting formula: * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); */ uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1); uint32_t priDiv = baudRate_Bps * quantum; /* Assertion: Desired baud rate is too high. */ assert(baudRate_Bps <= 1000000U); /* Assertion: Source clock should greater than baud rate * quantum. */ assert(priDiv <= sourceClock_Hz); if (0 == priDiv) { priDiv = 1; } priDiv = (sourceClock_Hz / priDiv) - 1; /* Desired baud rate is too low. */ if (priDiv > 0xFF) { priDiv = 0xFF; } timingConfig.preDivider = priDiv; /* Update actual timing characteristic. */ FLEXCAN_SetTimingConfig(base, &timingConfig); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig) { /* FlexCAN FD timing setting formula: * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; */ uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg; uint32_t priDiv = baudRateFD_Bps * quantum; /* Assertion: Desired baud rate is too high. */ assert(baudRateFD_Bps <= 8000000U); /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ assert(priDiv <= sourceClock_Hz); if (0 == priDiv) { priDiv = 1; } priDiv = (sourceClock_Hz / priDiv) - 1; /* Desired baud rate is too low. */ if (priDiv > 0xFF) { priDiv = 0xFF; } timingConfig.fpreDivider = priDiv; /* Update actual timing characteristic. */ FLEXCAN_SetFDTimingConfig(base, &timingConfig); } #endif /*! * brief Initializes a FlexCAN instance. * * This function initializes the FlexCAN module with user-defined settings. * This example shows how to set up the flexcan_config_t parameters and how * to call the FLEXCAN_Init function by passing in these parameters. * code * flexcan_config_t flexcanConfig; * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 1000000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.enableDoze = false; * flexcanConfig.timingConfig = timingConfig; * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); * endcode * * param base FlexCAN peripheral base address. * param config Pointer to the user-defined configuration structure. * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. */ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) { uint32_t mcrTemp; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance; #endif /* Assertion. */ assert(config); assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) instance = FLEXCAN_GetInstance(base); /* Enable FlexCAN clock. */ CLOCK_EnableClock(s_flexcanClock[instance]); #if defined(FLEXCAN_PERIPH_CLOCKS) /* Enable FlexCAN serial clock. */ CLOCK_EnableClock(s_flexcanPeriphClock[instance]); #endif /* FLEXCAN_PERIPH_CLOCKS */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE /* Disable FlexCAN Module. */ FLEXCAN_Enable(base, false); /* Protocol-Engine clock source selection, This bit must be set * when FlexCAN Module in Disable Mode. */ base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; #else #if defined(CAN_CTRL1_CLKSRC_MASK) if (!FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) { /* Disable FlexCAN Module. */ FLEXCAN_Enable(base, false); /* Protocol-Engine clock source selection, This bit must be set * when FlexCAN Module in Disable Mode. */ base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; } #endif #endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ /* Enable FlexCAN Module for configuration. */ FLEXCAN_Enable(base, true); /* Reset to known status. */ FLEXCAN_Reset(base); /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ mcrTemp = base->MCR; /* Set the maximum number of Message Buffers */ mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1); /* Enable Loop Back Mode? */ base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; /* Enable Timer Sync? */ base->CTRL1 = (config->enableTimerSync) ? base->CTRL1 | CAN_CTRL1_TSYN_MASK : base->CTRL1 & ~CAN_CTRL1_TSYN_MASK; /* Enable Self Wake Up Mode and configure the wake up source. */ mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; mcrTemp = (kFLEXCAN_WakeupSrcFiltered == config->wakeupSrc) ? mcrTemp | CAN_MCR_WAKSRC_MASK : mcrTemp & ~CAN_MCR_WAKSRC_MASK; /* Enable Individual Rx Masking? */ mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) { /* Enable Doze Mode? */ mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; } #endif /* Save MCR Configuration. */ base->MCR = mcrTemp; /* Baud Rate Configuration.*/ FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Initializes a FlexCAN instance. * * This function initializes the FlexCAN module with user-defined settings. * This example shows how to set up the flexcan_config_t parameters and how * to call the FLEXCAN_FDInit function by passing in these parameters. * code * flexcan_config_t flexcanConfig; * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig.baudRate = 1000000U; * flexcanConfig.baudRateFD = 2000000U; * flexcanConfig.maxMbNum = 16; * flexcanConfig.enableLoopBack = false; * flexcanConfig.enableSelfWakeup = false; * flexcanConfig.enableIndividMask = false; * flexcanConfig.enableDoze = false; * flexcanConfig.timingConfig = timingConfig; * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); * endcode * * param base FlexCAN peripheral base address. * param config Pointer to the user-defined configuration structure. * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. * param dataSize FlexCAN FD frame payload size. * param brs If bitrate switch is enabled in FD mode. */ void FLEXCAN_FDInit( CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) { assert(dataSize <= 3U); /* Initialization of classical CAN. */ FLEXCAN_Init(base, config, sourceClock_Hz); /* Extra bitrate setting for CANFD. */ FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); /* Enable FD operation and set bitrate switch. */ if (brs) { base->FDCTRL &= CAN_FDCTRL_FDRATE_MASK; } else { base->FDCTRL &= ~CAN_FDCTRL_FDRATE_MASK; } /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); if (brs && (!config->enableLoopBack)) { base->FDCTRL |= CAN_FDCTRL_TDCEN_MASK | CAN_FDCTRL_TDCOFF(0x2U); } base->MCR |= CAN_MCR_FDEN_MASK; base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize); #if defined(CAN_FDCTRL_MBDSR1_MASK) base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize); #endif #if defined(CAN_FDCTRL_MBDSR2_MASK) base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize); #endif #if defined(CAN_FDCTRL_MBDSR3_MASK) base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize); #endif /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } #endif /*! * brief De-initializes a FlexCAN instance. * * This function disables the FlexCAN module clock and sets all register values * to the reset value. * * param base FlexCAN peripheral base address. */ void FLEXCAN_Deinit(CAN_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) uint32_t instance; #endif /* Reset all Register Contents. */ FLEXCAN_Reset(base); /* Disable FlexCAN module. */ FLEXCAN_Enable(base, false); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) instance = FLEXCAN_GetInstance(base); #if defined(FLEXCAN_PERIPH_CLOCKS) /* Disable FlexCAN serial clock. */ CLOCK_DisableClock(s_flexcanPeriphClock[instance]); #endif /* FLEXCAN_PERIPH_CLOCKS */ /* Disable FlexCAN clock. */ CLOCK_DisableClock(s_flexcanClock[instance]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } /*! * brief Gets the default configuration structure. * * This function initializes the FlexCAN configuration structure to default values. The default * values are as follows. * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; * flexcanConfig->baudRate = 1000000U; * flexcanConfig->baudRateFD = 2000000U; * flexcanConfig->maxMbNum = 16; * flexcanConfig->enableLoopBack = false; * flexcanConfig->enableSelfWakeup = false; * flexcanConfig->enableIndividMask = false; * flexcanConfig->enableDoze = false; * flexcanConfig.timingConfig = timingConfig; * * param config Pointer to the FlexCAN configuration structure. */ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) { /* Assertion. */ assert(config); /* Initializes the configure structure to zero. */ memset(config, 0, sizeof(*config)); /* Initialize FlexCAN Module config struct with default value. */ config->clkSrc = kFLEXCAN_ClkSrcOsc; config->baudRate = 1000000U; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) config->baudRateFD = 2000000U; #endif config->maxMbNum = 16; config->enableLoopBack = false; config->enableTimerSync = true; config->enableSelfWakeup = false; config->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; config->enableIndividMask = false; #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) config->enableDoze = false; #endif /* Default protocol timing configuration, time quantum is 10. */ config->timingConfig.phaseSeg1 = 3; config->timingConfig.phaseSeg2 = 2; config->timingConfig.propSeg = 1; config->timingConfig.rJumpwidth = 1; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) config->timingConfig.fphaseSeg1 = 3; config->timingConfig.fphaseSeg2 = 3; config->timingConfig.fpropSeg = 1; config->timingConfig.frJumpwidth = 1; #endif } /*! * brief Sets the FlexCAN protocol timing characteristic. * * This function gives user settings to CAN bus timing characteristic. * The function is for an experienced user. For less experienced users, call * the FLEXCAN_Init() and fill the baud rate field with a desired value. * This provides the default timing characteristics to the module. * * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set * in FLEXCAN_Init(). * * param base FlexCAN peripheral base address. * param config Pointer to the timing configuration structure. */ void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ assert(config); /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) if (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) { /* Cleaning previous Timing Setting. */ base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | CAN_CBT_EPROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ base->CBT |= (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | CAN_CBT_EPSEG1(config->phaseSeg1) | CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); } else { /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_PROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); } #else /* Cleaning previous Timing Setting. */ base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_PROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); #endif /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Sets the FlexCAN FD protocol timing characteristic. * * This function gives user settings to CAN bus timing characteristic. * The function is for an experienced user. For less experienced users, call * the FLEXCAN_Init() and fill the baud rate field with a desired value. * This provides the default timing characteristics to the module. * * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set * in FLEXCAN_Init(). * * param base FlexCAN peripheral base address. * param config Pointer to the timing configuration structure. */ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) { /* Assertion. */ assert(config); /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); base->CBT |= CAN_CBT_BTF(1); /* Cleaning previous Timing Setting. */ base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK); /* Updating Timing Setting according to configuration structure. */ base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | CAN_FDCBT_FPROPSEG(config->fpropSeg)); /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } #endif /*! * brief Sets the FlexCAN receive message buffer global mask. * * This function sets the global mask for the FlexCAN message buffer in a matching process. * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). * * param base FlexCAN peripheral base address. * param mask Rx Message Buffer Global Mask value. */ void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); /* Setting Rx Message Buffer Global Mask value. */ base->RXMGMASK = mask; base->RX14MASK = mask; base->RX15MASK = mask; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } /*! * brief Sets the FlexCAN receive FIFO global mask. * * This function sets the global mask for FlexCAN FIFO in a matching process. * * param base FlexCAN peripheral base address. * param mask Rx Fifo Global Mask value. */ void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) { /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); /* Setting Rx FIFO Global Mask value. */ base->RXFGMASK = mask; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } /*! * brief Sets the FlexCAN receive individual mask. * * This function sets the individual mask for the FlexCAN matching process. * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to * the Rx Filter with the same index. Note that only the first 32 * individual masks can be used as the Rx FIFO filter mask. * * param base FlexCAN peripheral base address. * param maskIdx The Index of individual Mask. * param mask Rx Individual Mask value. */ void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) { assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); /* Setting Rx Individual Mask value. */ base->RXIMR[maskIdx] = mask; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } /*! * brief Configures a FlexCAN transmit message buffer. * * This function aborts the previous transmission, cleans the Message Buffer, and * configures it as a Transmit Message Buffer. * * param base FlexCAN peripheral base address. * param mbIdx The Message Buffer index. * param enable Enable/disable Tx Message Buffer. * - true: Enable Tx Message Buffer. * - false: Disable Tx Message Buffer. */ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Inactivate Message Buffer. */ if (enable) { base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); } else { base->MB[mbIdx].CS = 0; } /* Clean Message Buffer content. */ base->MB[mbIdx].ID = 0x0; base->MB[mbIdx].WORD0 = 0x0; base->MB[mbIdx].WORD1 = 0x0; } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) { uint32_t dataSize; uint32_t offset = 0; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; switch (dataSize) { case kFLEXCAN_8BperMB: offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16; break; case kFLEXCAN_16BperMB: offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24; break; case kFLEXCAN_32BperMB: offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40; break; case kFLEXCAN_64BperMB: offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72; break; default: break; } /* To get the dword aligned offset, need to divide by 4. */ offset = offset / 4; return offset; } #endif #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Configures a FlexCAN transmit message buffer. * * This function aborts the previous transmission, cleans the Message Buffer, and * configures it as a Transmit Message Buffer. * * param base FlexCAN peripheral base address. * param mbIdx The Message Buffer index. * param enable Enable/disable Tx Message Buffer. * - true: Enable Tx Message Buffer. * - false: Disable Tx Message Buffer. */ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint8_t cnt = 0; uint8_t payload_dword = 1; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); #endif /* Inactivate Message Buffer. */ if (enable) { /* Inactivate by writing CS. */ mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); } else { mbAddr[offset] = 0x0; } /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 Bytes payload. */ for (cnt = 0; cnt < dataSize + 1; cnt++) { payload_dword *= 2; } /* Clean ID. */ mbAddr[offset + 1] = 0x0; /* Clean Message Buffer content, DWORD by DWORD. */ for (cnt = 0; cnt < payload_dword; cnt++) { mbAddr[offset + 2 + cnt] = 0x0; } #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif } #endif /*! * brief Configures a FlexCAN Receive Message Buffer. * * This function cleans a FlexCAN build-in Message Buffer and configures it * as a Receive Message Buffer. * * param base FlexCAN peripheral base address. * param mbIdx The Message Buffer index. * param config Pointer to the FlexCAN Message Buffer configuration structure. * param enable Enable/disable Rx Message Buffer. * - true: Enable Rx Message Buffer. * - false: Disable Rx Message Buffer. */ void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; /* Inactivate Message Buffer. */ base->MB[mbIdx].CS = 0; /* Clean Message Buffer content. */ base->MB[mbIdx].ID = 0x0; base->MB[mbIdx].WORD0 = 0x0; base->MB[mbIdx].WORD1 = 0x0; if (enable) { /* Setup Message Buffer ID. */ base->MB[mbIdx].ID = config->id; /* Setup Message Buffer format. */ if (kFLEXCAN_FrameFormatExtend == config->format) { cs_temp |= CAN_CS_IDE_MASK; } /* Setup Message Buffer type. */ if (kFLEXCAN_FrameTypeRemote == config->type) { cs_temp |= CAN_CS_RTR_MASK; } /* Activate Rx Message Buffer. */ cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); base->MB[mbIdx].CS = cs_temp; } } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Configures a FlexCAN Receive Message Buffer. * * This function cleans a FlexCAN build-in Message Buffer and configures it * as a Receive Message Buffer. * * param base FlexCAN peripheral base address. * param mbIdx The Message Buffer index. * param config Pointer to the FlexCAN Message Buffer configuration structure. * param enable Enable/disable Rx Message Buffer. * - true: Enable Rx Message Buffer. * - false: Disable Rx Message Buffer. */ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(((config) || (false == enable))); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; uint8_t cnt = 0; volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); /* Inactivate all mailboxes first, clean ID and Message Buffer content. */ for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++) { base->MB[cnt].CS = 0; base->MB[cnt].ID = 0; base->MB[cnt].WORD0 = 0; base->MB[cnt].WORD1 = 0; } if (enable) { /* Setup Message Buffer ID. */ mbAddr[offset + 1] = config->id; /* Setup Message Buffer format. */ if (kFLEXCAN_FrameFormatExtend == config->format) { cs_temp |= CAN_CS_IDE_MASK; } /* Activate Rx Message Buffer. */ cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); mbAddr[offset] = cs_temp; } } #endif /*! * brief Configures the FlexCAN Rx FIFO. * * This function configures the Rx FIFO with given Rx FIFO configuration. * * param base FlexCAN peripheral base address. * param config Pointer to the FlexCAN Rx FIFO configuration structure. * param enable Enable/disable Rx FIFO. * - true: Enable Rx FIFO. * - false: Disable Rx FIFO. */ void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) { /* Assertion. */ assert((config) || (false == enable)); volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); uint8_t setup_mb, i, rffn = 0; /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); if (enable) { assert(config->idFilterNum <= 128); /* Get the setup_mb value. */ setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT; setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? setup_mb : FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); /* Determine RFFN value. */ for (i = 0; i <= 0xF; i++) { if ((8 * (i + 1)) >= config->idFilterNum) { rffn = i; assert(((setup_mb - 8) - (2 * rffn)) > 0); base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); break; } } } else { rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; } /* Clean ID filter table occuyied Message Buffer Region. */ rffn = (rffn + 1) * 8; for (i = 0; i < rffn; i++) { idFilterRegion[i] = 0x0; } if (enable) { /* Disable unused Rx FIFO Filter. */ for (i = config->idFilterNum; i < rffn; i++) { idFilterRegion[i] = 0xFFFFFFFFU; } /* Copy ID filter table to Message Buffer Region. */ for (i = 0; i < config->idFilterNum; i++) { idFilterRegion[i] = config->idFilterTable[i]; } /* Setup ID Fitlter Type. */ switch (config->idFilterType) { case kFLEXCAN_RxFifoFilterTypeA: base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); break; case kFLEXCAN_RxFifoFilterTypeB: base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); break; case kFLEXCAN_RxFifoFilterTypeC: base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); break; case kFLEXCAN_RxFifoFilterTypeD: /* All frames rejected. */ base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); break; default: break; } /* Setting Message Reception Priority. */ base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK : base->CTRL2 | CAN_CTRL2_MRP_MASK; /* Enable Rx Message FIFO. */ base->MCR |= CAN_MCR_RFEN_MASK; } else { /* Disable Rx Message FIFO. */ base->MCR &= ~CAN_MCR_RFEN_MASK; /* Clean MB0 ~ MB5. */ FLEXCAN_SetRxMbConfig(base, 0, NULL, false); FLEXCAN_SetRxMbConfig(base, 1, NULL, false); FLEXCAN_SetRxMbConfig(base, 2, NULL, false); FLEXCAN_SetRxMbConfig(base, 3, NULL, false); FLEXCAN_SetRxMbConfig(base, 4, NULL, false); FLEXCAN_SetRxMbConfig(base, 5, NULL, false); } /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) /*! * brief Enables or disables the FlexCAN Rx FIFO DMA request. * * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. * * param base FlexCAN peripheral base address. * param enable true to enable, false to disable. */ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) { if (enable) { /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); /* Enable FlexCAN DMA. */ base->MCR |= CAN_MCR_DMA_MASK; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } else { /* Enter Freeze Mode. */ FLEXCAN_EnterFreezeMode(base); /* Disable FlexCAN DMA. */ base->MCR &= ~CAN_MCR_DMA_MASK; /* Exit Freeze Mode. */ FLEXCAN_ExitFreezeMode(base); } } #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) /*! * FlexCAN: A frame with wrong ID or payload is transmitted into * the CAN bus when the Message Buffer under transmission is * either aborted or deactivated while the CAN bus is in the Bus Idle state * * This function to do workaround for ERR006032 * * param base FlexCAN peripheral base address. * param mbIdx The FlexCAN Message Buffer index. */ static void FLEXCAN_ERRATA_6032(CAN_Type *base, uint8_t mbIdx) { uint32_t dbg_temp = 0U; volatile const uint32_t *dbg1Addr = &(base->MCR) + OFFSET_DBG1 / 4; /*after backup all interruption, disable ALL interruption*/ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) uint32_t u32TempIMASK2 = base->IMASK2; base->IMASK2 = 0; #endif uint32_t u32TempIMASK1 = base->IMASK1; base->IMASK1 = 0; dbg_temp = (uint32_t)(*dbg1Addr); switch (dbg_temp & CAN_DBG1_CBN_MASK) { case RXINTERMISSION: if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) { /*wait until CFSM is different from RXINTERMISSION */ while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == RXINTERMISSION) { __NOP(); } } break; case TXINTERMISSION: if ((dbg_temp & CAN_DBG1_CBN_MASK) == CBN_VALUE3) { /*wait until CFSM is different from TXINTERMISSION*/ while ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == TXINTERMISSION) { __NOP(); } } break; default: break; } /*Anyway, BUSIDLE need to delay*/ if ((((uint32_t)(*dbg1Addr)) & CAN_DBG1_CBN_MASK) == BUSIDLE) { uint32_t n = DELAY_BUSIDLE; while (n-- > 0) { __NOP(); } } /*Write 0x0 into Code field of CS word.*/ base->MB[mbIdx].CS &= ~CAN_CS_CODE_MASK; /*restore interruption*/ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) base->IMASK2 = u32TempIMASK2; #endif base->IMASK1 = u32TempIMASK1; } #endif /*! * brief Writes a FlexCAN Message to the Transmit Message Buffer. * * This function writes a CAN Message to the specified Transmit Message Buffer * and changes the Message Buffer state to start CAN Message transmit. After * that the function returns immediately. * * param base FlexCAN peripheral base address. * param mbIdx The FlexCAN Message Buffer index. * param txFrame Pointer to CAN message frame to be sent. * retval kStatus_Success - Write Tx Message Buffer Successfully. * retval kStatus_Fail - Tx Message Buffer is currently in use. */ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(txFrame->length <= 8); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) FLEXCAN_ERRATA_6032(base, mbIdx); #endif /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) { /* Inactive Tx Message Buffer. */ base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); /* Fill Message ID field. */ base->MB[mbIdx].ID = txFrame->id; /* Fill Message Format field. */ if (kFLEXCAN_FrameFormatExtend == txFrame->format) { cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; } /* Fill Message Type field. */ if (kFLEXCAN_FrameTypeRemote == txFrame->type) { cs_temp |= CAN_CS_RTR_MASK; } cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); /* Load Message Payload. */ base->MB[mbIdx].WORD0 = txFrame->dataWord0; base->MB[mbIdx].WORD1 = txFrame->dataWord1; /* Activate Tx Message Buffer. */ base->MB[mbIdx].CS = cs_temp; #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif return kStatus_Success; } else { /* Tx Message Buffer is activated, return immediately. */ return kStatus_Fail; } } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. * * This function writes a CAN FD Message to the specified Transmit Message Buffer * and changes the Message Buffer state to start CAN FD Message transmit. After * that the function returns immediately. * * param base FlexCAN peripheral base address. * param mbIdx The FlexCAN FD Message Buffer index. * param txFrame Pointer to CAN FD message frame to be sent. * retval kStatus_Success - Write Tx Message Buffer Successfully. * retval kStatus_Fail - Tx Message Buffer is currently in use. */ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(txFrame); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp = 0; uint8_t cnt = 0; uint32_t can_cs = 0; uint8_t payload_dword = 1; uint32_t dataSize; #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) FLEXCAN_ERRATA_6032(base, mbIdx); #endif dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); #endif volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); can_cs = mbAddr[0]; /* Check if Message Buffer is available. */ if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) { /* Inactive Tx Message Buffer and Fill Message ID field. */ mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); mbAddr[offset + 1] = txFrame->id; /* Fill Message Format field. */ if (kFLEXCAN_FrameFormatExtend == txFrame->format) { cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; } cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) | CAN_CS_BRS(txFrame->brs); /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 Bytes payload. */ for (cnt = 0; cnt < dataSize + 1; cnt++) { payload_dword *= 2; } /* Load Message Payload and Activate Tx Message Buffer. */ for (cnt = 0; cnt < payload_dword; cnt++) { mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt]; } mbAddr[offset] = cs_temp; #if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); #endif return kStatus_Success; } else { /* Tx Message Buffer is activated, return immediately. */ return kStatus_Fail; } } #endif /*! * brief Reads a FlexCAN Message from Receive Message Buffer. * * This function reads a CAN message from a specified Receive Message Buffer. * The function fills a receive CAN message frame structure with * just received data and activates the Message Buffer again. * The function returns immediately. * * param base FlexCAN peripheral base address. * param mbIdx The FlexCAN Message Buffer index. * param rxFrame Pointer to CAN message frame structure for reception. * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * retval kStatus_Fail - Rx Message Buffer is empty. */ status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[mbIdx].CS; /* Get Rx Message Buffer Code field. */ rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; /* Check to see if Rx Message Buffer is full. */ if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) { /* Store Message ID. */ rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); /* Get the message ID and format. */ rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; /* Get the message type. */ rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; /* Get the time stamp. */ rxFrame->timestamp = (cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT; /* Store Message Payload. */ rxFrame->dataWord0 = base->MB[mbIdx].WORD0; rxFrame->dataWord1 = base->MB[mbIdx].WORD1; /* Read free-running timer to unlock Rx Message Buffer. */ (void)base->TIMER; if (kFLEXCAN_RxMbFull == rx_code) { return kStatus_Success; } else { return kStatus_FLEXCAN_RxOverflow; } } else { /* Read free-running timer to unlock Rx Message Buffer. */ (void)base->TIMER; return kStatus_Fail; } } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Reads a FlexCAN FD Message from Receive Message Buffer. * * This function reads a CAN FD message from a specified Receive Message Buffer. * The function fills a receive CAN FD message frame structure with * just received data and activates the Message Buffer again. * The function returns immediately. * * param base FlexCAN peripheral base address. * param mbIdx The FlexCAN FD Message Buffer index. * param rxFrame Pointer to CAN FD message frame structure for reception. * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * retval kStatus_Fail - Rx Message Buffer is empty. */ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { /* Assertion. */ assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(rxFrame); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); uint32_t cs_temp; uint8_t rx_code; uint8_t cnt = 0; uint32_t can_id = 0; uint32_t dataSize; dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; uint8_t payload_dword = 1; volatile uint32_t *mbAddr = &(base->MB[0].CS); uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = mbAddr[offset]; can_id = mbAddr[offset + 1]; /* Get Rx Message Buffer Code field. */ rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; /* Check to see if Rx Message Buffer is full. */ if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) { /* Store Message ID. */ rxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); /* Get the message ID and format. */ rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; /* Get the message type. */ rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; /* Get the time stamp. */ rxFrame->timestamp = (cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT; /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 Bytes payload. */ for (cnt = 0; cnt < dataSize + 1; cnt++) { payload_dword *= 2; } /* Store Message Payload. */ for (cnt = 0; cnt < payload_dword; cnt++) { rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt]; } /* Read free-running timer to unlock Rx Message Buffer. */ (void)base->TIMER; if (kFLEXCAN_RxMbFull == rx_code) { return kStatus_Success; } else { return kStatus_FLEXCAN_RxOverflow; } } else { /* Read free-running timer to unlock Rx Message Buffer. */ (void)base->TIMER; return kStatus_Fail; } } #endif /*! * brief Reads a FlexCAN Message from Rx FIFO. * * This function reads a CAN message from the FlexCAN build-in Rx FIFO. * * param base FlexCAN peripheral base address. * param rxFrame Pointer to CAN message frame structure for reception. * retval kStatus_Success - Read Message from Rx FIFO successfully. * retval kStatus_Fail - Rx FIFO is not enabled. */ status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) { /* Assertion. */ assert(rxFrame); uint32_t cs_temp; /* Check if Rx FIFO is Enabled. */ if (base->MCR & CAN_MCR_RFEN_MASK) { /* Read CS field of Rx Message Buffer to lock Message Buffer. */ cs_temp = base->MB[0].CS; /* Read data from Rx FIFO output port. */ /* Store Message ID. */ rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); /* Get the message ID and format. */ rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; /* Get the message type. */ rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; /* Get the message length. */ rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; /* Store Message Payload. */ rxFrame->dataWord0 = base->MB[0].WORD0; rxFrame->dataWord1 = base->MB[0].WORD1; /* Store ID Filter Hit Index. */ rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); /* Read free-running timer to unlock Rx Message Buffer. */ (void)base->TIMER; return kStatus_Success; } else { return kStatus_Fail; } } /*! * brief Performs a polling send transaction on the CAN bus. * * Note that a transfer handle does not need to be created before calling this API. * * param base FlexCAN peripheral base pointer. * param mbIdx The FlexCAN Message Buffer index. * param txFrame Pointer to CAN message frame to be sent. * retval kStatus_Success - Write Tx Message Buffer Successfully. * retval kStatus_Fail - Tx Message Buffer is currently in use. */ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) { /* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) #endif { } /* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); #endif return kStatus_Success; } else { return kStatus_Fail; } } /*! * brief Performs a polling receive transaction on the CAN bus. * * Note that a transfer handle does not need to be created before calling this API. * * param base FlexCAN peripheral base pointer. * param mbIdx The FlexCAN Message Buffer index. * param rxFrame Pointer to CAN message frame structure for reception. * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * retval kStatus_Fail - Rx Message Buffer is empty. */ status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) #endif { } /* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); #endif /* Read Received CAN Message. */ return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Performs a polling send transaction on the CAN bus. * * Note that a transfer handle does not need to be created before calling this API. * * param base FlexCAN peripheral base pointer. * param mbIdx The FlexCAN FD Message Buffer index. * param txFrame Pointer to CAN FD message frame to be sent. * retval kStatus_Success - Write Tx Message Buffer Successfully. * retval kStatus_Fail - Tx Message Buffer is currently in use. */ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) { /* Write Tx Message Buffer to initiate a data sending. */ if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, txFrame)) { /* Wait until CAN Message send out. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) #endif { } /* Clean Tx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); #endif return kStatus_Success; } else { return kStatus_Fail; } } /*! * brief Performs a polling receive transaction on the CAN bus. * * Note that a transfer handle does not need to be created before calling this API. * * param base FlexCAN peripheral base pointer. * param mbIdx The FlexCAN FD Message Buffer index. * param rxFrame Pointer to CAN FD message frame structure for reception. * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. * retval kStatus_Fail - Rx Message Buffer is empty. */ status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) { /* Wait until Rx Message Buffer non-empty. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while (!FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << mbIdx)) #else while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) #endif { } /* Clean Rx Message Buffer Flag. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << mbIdx); #else FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); #endif /* Read Received CAN Message. */ return FLEXCAN_ReadFDRxMb(base, mbIdx, rxFrame); } #endif /*! * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. * * Note that a transfer handle does not need to be created before calling this API. * * param base FlexCAN peripheral base pointer. * param rxFrame Pointer to CAN message frame structure for reception. * retval kStatus_Success - Read Message from Rx FIFO successfully. * retval kStatus_Fail - Rx FIFO is not enabled. */ status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) { status_t rxFifoStatus; /* Wait until Rx FIFO non-empty. */ while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag)) { } /* */ rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); /* Clean Rx Fifo available flag. */ FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); return rxFifoStatus; } /*! * brief Initializes the FlexCAN handle. * * This function initializes the FlexCAN handle, which can be used for other FlexCAN * transactional APIs. Usually, for a specified FlexCAN instance, * call this API once to get the initialized handle. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param callback The callback function. * param userData The parameter of the callback function. */ void FLEXCAN_TransferCreateHandle(CAN_Type *base, flexcan_handle_t *handle, flexcan_transfer_callback_t callback, void *userData) { assert(handle); uint8_t instance; /* Clean FlexCAN transfer handle. */ memset(handle, 0, sizeof(*handle)); /* Get instance from peripheral base address. */ instance = FLEXCAN_GetInstance(base); /* Save the context in global variables to support the double weak mechanism. */ s_flexcanHandle[instance] = handle; /* Register Callback function. */ handle->callback = callback; handle->userData = userData; s_flexcanIsr = FLEXCAN_TransferHandleIRQ; /* We Enable Error & Status interrupt here, because this interrupt just * report current status of FlexCAN module through Callback function. * It is insignificance without a available callback function. */ if (handle->callback != NULL) { FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | kFLEXCAN_WakeUpInterruptEnable); } else { FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | kFLEXCAN_WakeUpInterruptEnable); } /* Enable interrupts in NVIC. */ EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); } /*! * brief Sends a message using IRQ. * * This function sends a message using IRQ. This is a non-blocking function, which returns * right away. When messages have been sent out, the send callback function is called. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. * retval kStatus_Success Start Tx Message Buffer sending process successfully. * retval kStatus_Fail Write Tx Message Buffer failed. * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. */ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) { /* Distinguish transmit type. */ if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; /* Register user Frame buffer to receive remote Frame. */ handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; } else { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; } if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) { /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); #endif return kStatus_Success; } else { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; return kStatus_Fail; } } else { return kStatus_FLEXCAN_TxBusy; } } /*! * brief Receives a message using IRQ. * * This function receives a message using IRQ. This is non-blocking function, which returns * right away. When the message has been received, the receive callback function is called. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. */ status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; /* Register Message Buffer. */ handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); #endif return kStatus_Success; } else { return kStatus_FLEXCAN_RxBusy; } } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Sends a message using IRQ. * * This function sends a message using IRQ. This is a non-blocking function, which returns * right away. When messages have been sent out, the send callback function is called. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. * retval kStatus_Success Start Tx Message Buffer sending process successfully. * retval kStatus_Fail Write Tx Message Buffer failed. * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. */ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) { /* Distinguish transmit type. */ if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; /* Register user Frame buffer to receive remote Frame. */ handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; } else { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; } if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, xfer->framefd)) { /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); #endif return kStatus_Success; } else { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; return kStatus_Fail; } } else { return kStatus_FLEXCAN_TxBusy; } } /*! * brief Receives a message using IRQ. * * This function receives a message using IRQ. This is non-blocking function, which returns * right away. When the message has been received, the receive callback function is called. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. */ status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) { /* Assertion. */ assert(handle); assert(xfer); assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) { handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; /* Register Message Buffer. */ handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; /* Enable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_EnableMbInterrupts(base, (uint64_t)1 << xfer->mbIdx); #else FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); #endif return kStatus_Success; } else { return kStatus_FLEXCAN_RxBusy; } } #endif /*! * brief Receives a message from Rx FIFO using IRQ. * * This function receives a message using IRQ. This is a non-blocking function, which returns * right away. When all messages have been received, the receive callback function is called. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param xfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. * retval kStatus_Success - Start Rx FIFO receiving process successfully. * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. */ status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) { /* Assertion. */ assert(handle); assert(xfer); /* Check if Message Buffer is idle. */ if (kFLEXCAN_StateIdle == handle->rxFifoState) { handle->rxFifoState = kFLEXCAN_StateRxFifo; /* Register Message Buffer. */ handle->rxFifoFrameBuf = xfer->frame; /* Enable Message Buffer Interrupt. */ FLEXCAN_EnableMbInterrupts( base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); return kStatus_Success; } else { return kStatus_FLEXCAN_RxFifoBusy; } } /*! * brief Aborts the interrupt driven message send process. * * This function aborts the interrupt driven message send process. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param mbIdx The FlexCAN Message Buffer index. */ void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); #endif /* Un-register handle. */ handle->mbFrameBuf[mbIdx] = 0x0; /* Clean Message Buffer. */ FLEXCAN_SetTxMbConfig(base, mbIdx, true); handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) /*! * brief Aborts the interrupt driven message send process. * * This function aborts the interrupt driven message send process. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param mbIdx The FlexCAN FD Message Buffer index. */ void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); #endif /* Un-register handle. */ handle->mbFDFrameBuf[mbIdx] = 0x0; /* Clean Message Buffer. */ FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); #endif /* Un-register handle. */ handle->mbFDFrameBuf[mbIdx] = 0x0; handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } #endif /*! * brief Aborts the interrupt driven message receive process. * * This function aborts the interrupt driven message receive process. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. * param mbIdx The FlexCAN Message Buffer index. */ void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) { /* Assertion. */ assert(handle); assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); /* Disable Message Buffer Interrupt. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_DisableMbInterrupts(base, (uint64_t)1 << mbIdx); #else FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); #endif /* Un-register handle. */ handle->mbFrameBuf[mbIdx] = 0x0; handle->mbState[mbIdx] = kFLEXCAN_StateIdle; } /*! * brief Aborts the interrupt driven message receive from Rx FIFO process. * * This function aborts the interrupt driven message receive from Rx FIFO process. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. */ void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ assert(handle); /* Check if Rx FIFO is enabled. */ if (base->MCR & CAN_MCR_RFEN_MASK) { /* Disable Rx Message FIFO Interrupts. */ FLEXCAN_DisableMbInterrupts( base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); /* Un-register handle. */ handle->rxFifoFrameBuf = 0x0; } handle->rxFifoState = kFLEXCAN_StateIdle; } /*! * brief FlexCAN IRQ handle function. * * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. * * param base FlexCAN peripheral base address. * param handle FlexCAN handle pointer. */ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) { /* Assertion. */ assert(handle); status_t status = kStatus_FLEXCAN_UnHandled; uint32_t result; /* Store Current FlexCAN Module Error and Status. */ result = base->ESR1; do { /* Solve FlexCAN Error and Status Interrupt. */ if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag)) { status = kStatus_FLEXCAN_ErrorStatus; /* Clear FlexCAN Error and Status Interrupt. */ FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag); } else if (result & kFLEXCAN_WakeUpIntFlag) { status = kStatus_FLEXCAN_WakeUp; FLEXCAN_ClearStatusFlags(base, kFLEXCAN_WakeUpIntFlag); } /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ else { /* For this implementation, we solve the Message with lowest MB index first. */ for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) { /* Get the lowest unhandled Message Buffer */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) if ((FLEXCAN_GetMbStatusFlags(base, (uint64_t)1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) #else if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) #endif { break; } } /* Does not find Message to deal with. */ if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) { break; } /* Solve Rx FIFO interrupt. */ if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag)) { switch (1 << result) { case kFLEXCAN_RxFifoOverflowFlag: status = kStatus_FLEXCAN_RxFifoOverflow; break; case kFLEXCAN_RxFifoWarningFlag: status = kStatus_FLEXCAN_RxFifoWarning; break; case kFLEXCAN_RxFifoFrameAvlFlag: status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxFifoIdle; } FLEXCAN_TransferAbortReceiveFifo(base, handle); break; default: status = kStatus_FLEXCAN_UnHandled; break; } } else { /* Get current State of Message Buffer. */ switch (handle->mbState[result]) { /* Solve Rx Data Frame. */ case kFLEXCAN_StateRxData: #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) if (base->MCR & CAN_MCR_FDEN_MASK) { status = FLEXCAN_ReadFDRxMb(base, result, handle->mbFDFrameBuf[result]); } else { status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); } #else status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); #endif if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxIdle; } #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) if (base->MCR & CAN_MCR_FDEN_MASK) { FLEXCAN_TransferFDAbortReceive(base, handle, result); } else { FLEXCAN_TransferAbortReceive(base, handle, result); } #else FLEXCAN_TransferAbortReceive(base, handle, result); #endif break; /* Solve Rx Remote Frame. */ case kFLEXCAN_StateRxRemote: status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); if (kStatus_Success == status) { status = kStatus_FLEXCAN_RxIdle; } FLEXCAN_TransferAbortReceive(base, handle, result); break; /* Solve Tx Data Frame. */ case kFLEXCAN_StateTxData: status = kStatus_FLEXCAN_TxIdle; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) if (base->MCR & CAN_MCR_FDEN_MASK) { FLEXCAN_TransferFDAbortSend(base, handle, result); } else { FLEXCAN_TransferAbortSend(base, handle, result); } #else FLEXCAN_TransferAbortSend(base, handle, result); #endif break; /* Solve Tx Remote Frame. */ case kFLEXCAN_StateTxRemote: handle->mbState[result] = kFLEXCAN_StateRxRemote; status = kStatus_FLEXCAN_TxSwitchToRx; #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) if (base->MCR & CAN_MCR_FDEN_MASK) { FLEXCAN_TransferFDAbortReceive(base, handle, result); } else { FLEXCAN_TransferAbortReceive(base, handle, result); } #else FLEXCAN_TransferAbortReceive(base, handle, result); #endif break; default: status = kStatus_FLEXCAN_UnHandled; break; } } /* Clear resolved Message Buffer IRQ. */ #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1 << result); #else FLEXCAN_ClearMbStatusFlags(base, 1 << result); #endif } /* Calling Callback Function if has one. */ if (handle->callback != NULL) { handle->callback(base, handle, status, result, handle->userData); } /* Reset return status */ status = kStatus_FLEXCAN_UnHandled; /* Store Current FlexCAN Module Error and Status. */ result = base->ESR1; } #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); #else while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); #endif } #if defined(CAN0) void CAN0_DriverIRQHandler(void) { assert(s_flexcanHandle[0]); s_flexcanIsr(CAN0, s_flexcanHandle[0]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(CAN1) void CAN1_DriverIRQHandler(void) { assert(s_flexcanHandle[1]); s_flexcanIsr(CAN1, s_flexcanHandle[1]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(CAN2) void CAN2_DriverIRQHandler(void) { assert(s_flexcanHandle[2]); s_flexcanIsr(CAN2, s_flexcanHandle[2]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(CAN3) void CAN3_DriverIRQHandler(void) { assert(s_flexcanHandle[3]); s_flexcanIsr(CAN3, s_flexcanHandle[3]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(CAN4) void CAN4_DriverIRQHandler(void) { assert(s_flexcanHandle[4]); s_flexcanIsr(CAN4, s_flexcanHandle[4]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(DMA__CAN0) void DMA_FLEXCAN0_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(DMA__CAN1) void DMA_FLEXCAN1_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(DMA__CAN2) void DMA_FLEXCAN2_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(ADMA__CAN0) void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(ADMA__CAN1) void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif #if defined(ADMA__CAN2) void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) { assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping exception return operation might vector to incorrect interrupt */ #if defined __CORTEX_M && (__CORTEX_M == 4U) __DSB(); #endif } #endif |