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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 | /* * Copyright (c) 2015, Freescale Semiconductor, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. * * o Redistributions in binary form must reproduce the above copyright notice, this * list of conditions and the following disclaimer in the documentation and/or * other materials provided with the distribution. * * o Neither the name of Freescale Semiconductor, Inc. nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include "lmem.h" /******************************************************************************* * Definitions ******************************************************************************/ #define LMEM_CACHE_LINE_SIZE 32 /******************************************************************************* * Code ******************************************************************************/ /******************************************************************************* * System Cache control functions ******************************************************************************/ /*FUNCTION********************************************************************** * * Function Name : LMEM_EnableSystemCache * Description : This function enable the System Cache. * *END**************************************************************************/ void LMEM_EnableSystemCache(LMEM_Type *base) { /* set command to invalidate all ways */ /* and write GO bit to initiate command */ LMEM_PSCCR_REG(base) = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); /* Enable cache, enable write buffer */ LMEM_PSCCR_REG(base) = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_DisableSystemCache * Description : This function disable the System Cache. * *END**************************************************************************/ void LMEM_DisableSystemCache(LMEM_Type *base) { LMEM_PSCCR_REG(base) = 0x0; __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushSystemCache * Description : This function flush the System Cache. * *END**************************************************************************/ void LMEM_FlushSystemCache(LMEM_Type *base) { LMEM_PSCCR_REG(base) |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK ; LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushSystemCacheLine * Description : This function is called to push a line out of the System Cache. * *END**************************************************************************/ static void LMEM_FlushSystemCacheLine(LMEM_Type *base, void *address) { assert((uint32_t)address >= 0x20000000); /* Invalidate by physical address */ LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(2); /* Set physical address and activate command */ LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; /* wait until the command completes */ while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushSystemCacheLines * Description : This function is called to flush the System Cache by * performing cache copy-backs. It must determine how * many cache lines need to be copied back and then * perform the copy-backs. * *END**************************************************************************/ void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) { void *endAddress = (void *)((uint32_t)address + length); address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); do { LMEM_FlushSystemCacheLine(base, address); address = (void *) ((uint32_t)address + LMEM_CACHE_LINE_SIZE); } while (address < endAddress); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateSystemCache * Description : This function invalidate the System Cache. * *END**************************************************************************/ void LMEM_InvalidateSystemCache(LMEM_Type *base) { LMEM_PSCCR_REG(base) |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK; LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateSystemCacheLine * Description : This function is called to invalidate a line out of * the System Cache. * *END**************************************************************************/ static void LMEM_InvalidateSystemCacheLine(LMEM_Type *base, void *address) { assert((uint32_t)address >= 0x20000000); /* Invalidate by physical address */ LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(1); /* Set physical address and activate command */ LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; /* wait until the command completes */ while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateSystemCacheLines * Description : This function is responsible for performing an data * cache invalidate. It must determine how many cache * lines need to be invalidated and then perform the * invalidation. * *END**************************************************************************/ void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) { void *endAddress = (void *)((uint32_t)address + length); address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); do { LMEM_InvalidateSystemCacheLine(base, address); address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); } while (address < endAddress); __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_EnableCodeCache * Description : This function enable the Code Cache. * *END**************************************************************************/ void LMEM_EnableCodeCache(LMEM_Type *base) { /* set command to invalidate all ways, enable write buffer */ /* and write GO bit to initiate command */ LMEM_PCCCR_REG(base) = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); /* Enable cache, enable write buffer */ LMEM_PCCCR_REG(base) = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_DisableCodeCache * Description : This function disable the Code Cache. * *END**************************************************************************/ void LMEM_DisableCodeCache(LMEM_Type *base) { LMEM_PCCCR_REG(base) = 0x0; __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushCodeCache * Description : This function flush the Code Cache. * *END**************************************************************************/ void LMEM_FlushCodeCache(LMEM_Type *base) { LMEM_PCCCR_REG(base) |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK; LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushCodeCacheLine * Description : This function is called to push a line out of the * Code Cache. * *END**************************************************************************/ static void LMEM_FlushCodeCacheLine(LMEM_Type *base, void *address) { assert((uint32_t)address < 0x20000000); /* Invalidate by physical address */ LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(2); /* Set physical address and activate command */ LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; /* wait until the command completes */ while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_FlushCodeCacheLines * Description : This function is called to flush the instruction * cache by performing cache copy-backs. It must * determine how many cache lines need to be copied * back and then perform the copy-backs. * *END**************************************************************************/ void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) { void *endAddress = (void *)((uint32_t)address + length); address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); do { LMEM_FlushCodeCacheLine(base, address); address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); } while (address < endAddress); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateCodeCache * Description : This function invalidate the Code Cache. * *END**************************************************************************/ void LMEM_InvalidateCodeCache(LMEM_Type *base) { LMEM_PCCCR_REG(base) |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK; LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; /* wait until the command completes */ while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); __ISB(); __DSB(); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateCodeCacheLine * Description : This function is called to invalidate a line out * of the Code Cache. * *END**************************************************************************/ static void LMEM_InvalidateCodeCacheLine(LMEM_Type *base, void *address) { assert((uint32_t)address < 0x20000000); /* Invalidate by physical address */ LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(1); /* Set physical address and activate command */ LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; /* wait until the command completes */ while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); } /*FUNCTION********************************************************************** * * Function Name : LMEM_InvalidateCodeCacheLines * Description : This function is responsible for performing an * Code Cache invalidate. It must determine * how many cache lines need to be invalidated and then * perform the invalidation. * *END**************************************************************************/ void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) { void *endAddress = (void *)((uint32_t)address + length); address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); do { LMEM_InvalidateCodeCacheLine(base, address); address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); } while (address < endAddress); __ISB(); __DSB(); } /******************************************************************************* * EOF ******************************************************************************/ |