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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 | /* * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> * Copyright (c) 2017 Linaro Limited * Copyright (c) 2017 BayLibre, SAS * * SPDX-License-Identifier: Apache-2.0 */ #define LOG_DOMAIN flash_stm32g0 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL #include <logging/log.h> LOG_MODULE_REGISTER(LOG_DOMAIN); #include <kernel.h> #include <device.h> #include <string.h> #include <flash.h> #include <init.h> #include <soc.h> #include "flash_stm32.h" #define STM32G0X_PAGE_SHIFT 11 /* * offset and len must be aligned on 8 for write, * positive and not beyond end of flash */ bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len, bool write) { return (!write || (offset % 8 == 0 && len % 8 == 0)) && flash_stm32_range_exists(dev, offset, len); } /* * STM32G0xx devices can have up to 64 2K pages */ static unsigned int get_page(off_t offset) { return offset >> STM32G0X_PAGE_SHIFT; } static int write_dword(struct device *dev, off_t offset, u64_t val) { volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS); struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev); u32_t tmp; int rc; /* if the control register is locked, do not fail silently */ if (regs->cr & FLASH_CR_LOCK) { return -EIO; } /* Check that no Flash main memory operation is ongoing */ rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } /* Check if this double word is erased */ if (flash[0] != 0xFFFFFFFFUL || flash[1] != 0xFFFFFFFFUL) { return -EIO; } /* Set the PG bit */ regs->cr |= FLASH_CR_PG; /* Flush the register write */ tmp = regs->cr; /* Perform the data write operation at the desired memory address */ flash[0] = (u32_t)val; flash[1] = (u32_t)(val >> 32); /* Wait until the BSY bit is cleared */ rc = flash_stm32_wait_flash_idle(dev); /* Clear the PG bit */ regs->cr &= (~FLASH_CR_PG); return rc; } static int erase_page(struct device *dev, unsigned int page) { struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev); u32_t tmp; int rc; /* if the control register is locked, do not fail silently */ if (regs->cr & FLASH_CR_LOCK) { return -EIO; } /* Check that no Flash memory operation is ongoing */ rc = flash_stm32_wait_flash_idle(dev); if (rc < 0) { return rc; } /* Set the PER bit and select the page you wish to erase */ regs->cr |= FLASH_CR_PER; regs->cr &= ~FLASH_CR_PNB_Msk; regs->cr |= ((page % 256) << 3); /* Set the STRT bit */ regs->cr |= FLASH_CR_STRT; /* flush the register write */ tmp = regs->cr; /* Wait for the BSY bit */ rc = flash_stm32_wait_flash_idle(dev); regs->cr &= ~FLASH_CR_PER; return rc; } int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset, unsigned int len) { int i, rc = 0; i = get_page(offset); for (; i <= get_page(offset + len - 1) ; ++i) { rc = erase_page(dev, i); if (rc < 0) { break; } } return rc; } int flash_stm32_write_range(struct device *dev, unsigned int offset, const void *data, unsigned int len) { int i, rc = 0; for (i = 0; i < len; i += 8, offset += 8) { rc = write_dword(dev, offset, ((const u64_t *) data)[i>>3]); if (rc < 0) { return rc; } } return rc; } void flash_stm32_page_layout(struct device *dev, const struct flash_pages_layout **layout, size_t *layout_size) { static struct flash_pages_layout stm32g0_flash_layout = { .pages_count = 0, .pages_size = 0, }; ARG_UNUSED(dev); if (stm32g0_flash_layout.pages_count == 0) { stm32g0_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE; stm32g0_flash_layout.pages_size = FLASH_PAGE_SIZE; } *layout = &stm32g0_flash_layout; *layout_size = 1; } |