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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 | /* * SPDX-License-Identifier: Apache-2.0 * * GPIO driver for the CC2650 SOC from Texas Instruments. */ #include <toolchain/gcc.h> #include <device.h> #include <gpio.h> #include <init.h> #include <soc.h> #include <sys_io.h> #include "gpio_utils.h" struct gpio_cc2650_data { u32_t pin_callback_enables; sys_slist_t callbacks; }; /* Pre-declarations */ static int gpio_cc2650_init(struct device *dev); static int gpio_cc2650_config(struct device *port, int access_op, u32_t pin, int flags); static int gpio_cc2650_write(struct device *port, int access_op, u32_t pin, u32_t value); static int gpio_cc2650_read(struct device *port, int access_op, u32_t pin, u32_t *value); static int gpio_cc2650_manage_callback(struct device *port, struct gpio_callback *callback, bool set); static int gpio_cc2650_enable_callback(struct device *port, int access_op, u32_t pin); static int gpio_cc2650_disable_callback(struct device *port, int access_op, u32_t pin); static u32_t gpio_cc2650_get_pending_int(struct device *dev); /* GPIO registers */ static const u32_t doutset31_0 = REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, CC2650_GPIO_DOUTSET31_0); static const u32_t doutclr31_0 = REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, CC2650_GPIO_DOUTCLR31_0); static const u32_t din31_0 = REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, CC2650_GPIO_DIN31_0); static const u32_t doe31_0 = REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, CC2650_GPIO_DOE31_0); static const u32_t evflags31_0 = REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS, CC2650_GPIO_EVFLAGS31_0); static struct gpio_cc2650_data gpio_cc2650_data = { .pin_callback_enables = 0 }; static const struct gpio_driver_api gpio_cc2650_funcs = { .config = gpio_cc2650_config, .write = gpio_cc2650_write, .read = gpio_cc2650_read, .manage_callback = gpio_cc2650_manage_callback, .enable_callback = gpio_cc2650_enable_callback, .disable_callback = gpio_cc2650_disable_callback, .get_pending_int = gpio_cc2650_get_pending_int }; DEVICE_AND_API_INIT(gpio_cc2650_0, CONFIG_GPIO_CC2650_NAME, gpio_cc2650_init, &gpio_cc2650_data, NULL, PRE_KERNEL_1, CONFIG_GPIO_CC2650_INIT_PRIO, &gpio_cc2650_funcs); static void disconnect(const int pin, u32_t *gpiodoe31_0, u32_t *iocfg) { *gpiodoe31_0 &= ~BIT(pin); *iocfg &= ~(CC2650_IOC_IOCFGX_PULL_CTL_MASK | CC2650_IOC_IOCFGX_IE_MASK); *iocfg |= CC2650_IOC_INPUT_DISABLED | CC2650_IOC_NO_PULL; } /* Configure a single pin. * If any asked option is not implementable, rollback entirely to * previous configuration. * * Note: For pin drive strength, the CC2650 devices only support * symmetric sink/source capabilities. * Thus, you may ONLY determine the common drive strength with * GPIO *low output state* flags. Flags for *high output state* * will be ignored. */ static int gpio_cc2650_config_pin(int pin, int flags) { const u32_t iocfg = REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS, CC2650_IOC_IOCFG0 + 0x4 * pin); u32_t iocfg_config = sys_read32(iocfg); u32_t gpio_doe31_0_config = sys_read32(doe31_0); /* Reset all configurable fields to 0 */ iocfg_config &= ~(CC2650_IOC_IOCFGX_IOSTR_MASK | CC2650_IOC_IOCFGX_PULL_CTL_MASK | CC2650_IOC_IOCFGX_EDGE_DET_MASK | CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK | CC2650_IOC_IOCFGX_IOMODE_MASK | CC2650_IOC_IOCFGX_IE_MASK | CC2650_IOC_IOCFGX_HYST_EN_MASK); if (flags & GPIO_PIN_DISABLE) { disconnect(pin, &gpio_doe31_0_config, &iocfg_config); goto commit_config; } if (flags & GPIO_DIR_OUT) { gpio_doe31_0_config |= BIT(pin); iocfg_config |= CC2650_IOC_INPUT_DISABLED; } else { gpio_doe31_0_config &= ~BIT(pin); iocfg_config |= CC2650_IOC_INPUT_ENABLED; } if (flags & GPIO_INT) { if (!(flags & GPIO_INT_EDGE) && !(flags & GPIO_INT_DOUBLE_EDGE)) { /* Can't do level-based interrupt */ /* Don't commit changes */ return -ENOTSUP; } iocfg_config |= BIT(CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS); if (flags & GPIO_INT_EDGE) { if (flags & GPIO_INT_ACTIVE_HIGH) { iocfg_config |= CC2650_IOC_POS_EDGE_DET; } else { iocfg_config |= CC2650_IOC_NEG_EDGE_DET; } } else if (flags & GPIO_INT_DOUBLE_EDGE) { iocfg_config |= CC2650_IOC_NEG_AND_POS_EDGE_DET; } if (flags & GPIO_INT_CLOCK_SYNC) { /* Don't commit changes */ return -ENOTSUP; } if (flags & GPIO_INT_DEBOUNCE) { iocfg_config |= CC2650_IOC_HYSTERESIS_ENABLED; } else { iocfg_config |= CC2650_IOC_HYSTERESIS_DISABLED; } } if (flags & GPIO_POL_INV) { iocfg_config |= CC2650_IOC_INVERTED_IO; } else { iocfg_config |= CC2650_IOC_NORMAL_IO; } if (flags & GPIO_PUD_PULL_UP) { iocfg_config |= CC2650_IOC_PULL_UP; } else if (flags & GPIO_PUD_PULL_DOWN) { iocfg_config |= CC2650_IOC_PULL_DOWN; } else { iocfg_config |= CC2650_IOC_NO_PULL; } /* Remember, we only look at GPIO_DS_*_LOW ! */ if (flags & GPIO_DS_DISCONNECT_LOW) { disconnect(pin, &gpio_doe31_0_config, &iocfg_config); } if (flags & GPIO_DS_ALT_LOW) { iocfg_config |= CC2650_IOC_MAX_DRIVE_STRENGTH; } else { iocfg_config |= CC2650_IOC_MIN_DRIVE_STRENGTH; } /* Commit changes */ commit_config: sys_write32(iocfg_config, iocfg); sys_write32(gpio_doe31_0_config, doe31_0); return 0; } static inline void gpio_cc2650_write_pin(int pin, u32_t value) { value ? sys_write32(BIT(pin), doutset31_0) : sys_write32(BIT(pin), doutclr31_0); } static inline void gpio_cc2650_read_pin(int pin, u32_t *value) { *value = sys_read32(din31_0) & BIT(pin); } static void gpio_cc2650_isr(void *arg) { struct device *dev = (struct device *)arg; struct gpio_cc2650_data *data = dev->driver_data; const u32_t events = sys_read32(evflags31_0); const u32_t call_mask = events & data->pin_callback_enables; /* Clear GPIO trigger events */ u32_t evflags = sys_read32(evflags31_0); sys_write32(evflags | call_mask, evflags31_0); _gpio_fire_callbacks(&data->callbacks, dev, call_mask); } static int gpio_cc2650_init(struct device *dev) { ARG_UNUSED(dev); /* ISR setup */ IRQ_CONNECT(TI_CC2650_GPIO_40022000_IRQ_0, TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY, gpio_cc2650_isr, DEVICE_GET(gpio_cc2650_0), 0); irq_enable(TI_CC2650_GPIO_40022000_IRQ_0); return 0; } static int gpio_cc2650_config(struct device *port, int access_op, u32_t pin, int flags) { ARG_UNUSED(port); if (access_op == GPIO_ACCESS_BY_PIN) { return gpio_cc2650_config_pin(pin, flags); } const u32_t nb_pins = 32; for (u8_t i = 0; i < nb_pins; ++i) { if (pin & 0x1 && gpio_cc2650_config_pin(i, flags) == -ENOTSUP) { /* The flags being treated the same for * every pin, if we get here then it's * necessarily the first pin on which we act. * * We expect gpio_cc2650_config_pin() to * NOT commit its changes if any problem * arises, thus we do nothing special here * to implement rollback to previous * configuration. */ return -ENOTSUP; } pin >>= 1; } return 0; } static int gpio_cc2650_write(struct device *port, int access_op, u32_t pin, u32_t value) { ARG_UNUSED(port); if (access_op == GPIO_ACCESS_BY_PIN) { gpio_cc2650_write_pin(pin, value); } else { const u32_t nb_pins = 32; for (u32_t i = 0; i < nb_pins; ++i) { if (pin & 0x1) { gpio_cc2650_write_pin(i, value); } pin >>= 1; } } return 0; } static int gpio_cc2650_read(struct device *port, int access_op, u32_t pin, u32_t *value) { ARG_UNUSED(port); if (access_op == GPIO_ACCESS_BY_PIN) { gpio_cc2650_read_pin(pin, value); *value >>= pin; } else { const u32_t nb_pins = 32; for (u32_t i = 0; i < nb_pins; ++i) { if (pin & 0x1) { gpio_cc2650_read_pin(i, value); } pin >>= 1; } } return 0; } static int gpio_cc2650_manage_callback(struct device *port, struct gpio_callback *callback, bool set) { struct gpio_cc2650_data *data = port->driver_data; _gpio_manage_callback(&data->callbacks, callback, set); return 0; } static int gpio_cc2650_enable_callback(struct device *port, int access_op, u32_t pin) { struct gpio_cc2650_data *data = port->driver_data; if (access_op == GPIO_ACCESS_BY_PIN) { data->pin_callback_enables |= BIT(pin); } else { data->pin_callback_enables |= pin; } return 0; } static int gpio_cc2650_disable_callback(struct device *port, int access_op, u32_t pin) { struct gpio_cc2650_data *data = port->driver_data; if (access_op == GPIO_ACCESS_BY_PIN) { data->pin_callback_enables &= ~BIT(pin); } else { data->pin_callback_enables &= ~pin; } return 0; } static u32_t gpio_cc2650_get_pending_int(struct device *dev) { ARG_UNUSED(dev); return sys_read32(evflags31_0); } |