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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 | /* * Copyright (c) 2016 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ /** * @file * @brief System/hardware module for Nordic Semiconductor nRF52 family processor * * This module provides routines to initialize and support board-level hardware * for the Nordic Semiconductor nRF52 family processor. */ #include <kernel.h> #include <device.h> #include <init.h> #include <soc.h> #include <cortex_m/exc.h> #ifdef CONFIG_RUNTIME_NMI extern void _NmiInit(void); #define NMI_INIT() _NmiInit() #else #define NMI_INIT() #endif #include "nrf.h" #define __SYSTEM_CLOCK_64M (64000000UL) #ifdef CONFIG_SOC_NRF52832 static bool ftpan_32(void) { if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { return true; } } return false; } static bool ftpan_37(void) { if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { return true; } } return false; } static bool ftpan_36(void) { if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) { if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) { return true; } } return false; } static void nordicsemi_nrf52832_init(void) { /* Workaround for FTPAN-32 "DIF: Debug session automatically * enables TracePort pins" found at Product Anomaly document * for your device located at https://www.nordicsemi.com/ */ if (ftpan_32()) { CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; } /* Workaround for FTPAN-37 "AMLI: EasyDMA is slow with Radio, * ECB, AAR and CCM." found at Product Anomaly document * for your device located at https://www.nordicsemi.com/ */ if (ftpan_37()) { *(volatile u32_t *)0x400005A0 = 0x3; } /* Workaround for FTPAN-36 "CLOCK: Some registers are not * reset when expected." found at Product Anomaly document * for your device located at https://www.nordicsemi.com/ */ if (ftpan_36()) { NRF_CLOCK->EVENTS_DONE = 0; NRF_CLOCK->EVENTS_CTTO = 0; } /* Configure GPIO pads as pPin Reset pin if Pin Reset * capabilities desired. If CONFIG_GPIO_AS_PINRESET is not * defined, pin reset will not be available. One GPIO (see * Product Specification to see which one) will then be * reserved for PinReset and not available as normal GPIO. */ #if defined(CONFIG_GPIO_AS_PINRESET) if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_UICR->PSELRESET[0] = 21; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_UICR->PSELRESET[1] = 21; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NVIC_SystemReset(); } #endif /* Enable SWO trace functionality. If ENABLE_SWO is not * defined, SWO pin will be used as GPIO (see Product * Specification to see which one). */ #if defined(ENABLE_SWO) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; #endif /* Enable Trace functionality. If ENABLE_TRACE is not * defined, TRACE pins will be used as GPIOs (see Product * Specification to see which ones). */ #if defined(ENABLE_TRACE) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; #endif } #endif /* CONFIG_SOC_NRF52832 */ #ifdef CONFIG_SOC_NRF52840 static bool errata_36(void) { if ((*(u32_t *)0x10000130ul == 0x8ul) && (*(u32_t *)0x10000134ul == 0x0ul)) { return true; } return false; } static bool errata_98(void) { if ((*(u32_t *)0x10000130ul == 0x8ul) && (*(u32_t *)0x10000134ul == 0x0ul)) { return true; } return false; } static bool errata_103(void) { if ((*(u32_t *)0x10000130ul == 0x8ul) && (*(u32_t *)0x10000134ul == 0x0ul)) { return true; } return false; } static bool errata_115(void) { if ((*(u32_t *)0x10000130ul == 0x8ul) && (*(u32_t *)0x10000134ul == 0x0ul)) { return true; } return false; } static bool errata_120(void) { if ((*(u32_t *)0x10000130ul == 0x8ul) && (*(u32_t *)0x10000134ul == 0x0ul)) { return true; } return false; } static void nordicsemi_nrf52840_init(void) { /* Workaround for Errata 36 "CLOCK: Some registers are not reset when * expected" found at the Errata document for your device located at * https://infocenter.nordicsemi.com/ */ if (errata_36()) { NRF_CLOCK->EVENTS_DONE = 0; NRF_CLOCK->EVENTS_CTTO = 0; NRF_CLOCK->CTIV = 0; } /* Workaround for Errata 98 "NFCT: Not able to communicate with the * peer" found at the Errata document for your device located at * https://infocenter.nordicsemi.com/ */ if (errata_98()) { *(volatile u32_t *)0x4000568Cul = 0x00038148ul; } /* Workaround for Errata 103 "CCM: Wrong reset value of CCM * MAXPACKETSIZE" found at the Errata document for your device * located at https://infocenter.nordicsemi.com/ */ if (errata_103()) { NRF_CCM->MAXPACKETSIZE = 0xFBul; } /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon * waking up from System ON Idle or System OFF mode" found at the * Errata document for your device located at * https://infocenter.nordicsemi.com/ */ if (errata_115()) { *(volatile u32_t *)0x40000EE4 = (*(volatile u32_t *) 0x40000EE4 & 0xFFFFFFF0) | (*(u32_t *)0x10000258 & 0x0000000F); } /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" * found at the Errata document for your device located at * https://infocenter.nordicsemi.com/ */ if (errata_120()) { *(volatile u32_t *)0x40029640ul = 0x200ul; } /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities * desired. * If CONFIG_GPIO_AS_PINRESET is not defined, pin reset will not be * available. One GPIO (see Product Specification to see which one) will * then be reserved for PinReset and not available as normal GPIO. */ #if defined(CONFIG_GPIO_AS_PINRESET) if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { } NRF_UICR->PSELRESET[0] = 18; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { } NRF_UICR->PSELRESET[1] = 18; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { } NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { } NVIC_SystemReset(); } #endif /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin * will be used as GPIO (see Product Specification to see which one). */ #if defined(ENABLE_SWO) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); #endif /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE * pins will be used as GPIOs (see Product Specification to see which * ones). */ #if defined(ENABLE_TRACE) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); #endif } #endif /* CONFIG_SOC_NRF52840 */ uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M; static void clock_init(void) { SystemCoreClock = __SYSTEM_CLOCK_64M; } static int nordicsemi_nrf52_init(struct device *arg) { u32_t key; ARG_UNUSED(arg); key = irq_lock(); #ifdef CONFIG_SOC_NRF52832 nordicsemi_nrf52832_init(); #endif #ifdef CONFIG_SOC_NRF52840 nordicsemi_nrf52840_init(); #endif /* Enable the FPU if the compiler used floating point unit * instructions. Since the FPU consumes energy, remember to * disable FPU use in the compiler if floating point unit * operations are not used in your code. */ #if defined(CONFIG_FLOAT) SCB->CPACR |= (3UL << 20) | (3UL << 22); __DSB(); __ISB(); #endif /* Configure NFCT pins as GPIOs if NFCT is not to be used in * your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, * two GPIOs (see Product Specification to see which ones) * will be reserved for NFC and will not be available as * normal GPIOs. */ #if defined(CONFIG_NFCT_PINS_AS_GPIOS) if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) { NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; while (NRF_NVMC->READY == NVMC_READY_READY_Busy) { ; } NVIC_SystemReset(); } #endif _ClearFaults(); /* Setup master clock */ clock_init(); /* Install default handler that simply resets the CPU * if configured in the kernel, NOP otherwise */ NMI_INIT(); irq_unlock(key); return 0; } SYS_INIT(nordicsemi_nrf52_init, PRE_KERNEL_1, 0); |