Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 | /* * Copyright (c) 2016 Open-RnD Sp. z o.o. * Copyright (c) 2016 Linaro Limited. * * SPDX-License-Identifier: Apache-2.0 */ /** * @brief Driver for UART port on STM32F10x family processor. * * Based on reference manual: * STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx * advanced ARM ® -based 32-bit MCUs * * Chapter 27: Universal synchronous asynchronous receiver * transmitter (USART) */ #include <kernel.h> #include <arch/cpu.h> #include <misc/__assert.h> #include <board.h> #include <init.h> #include <uart.h> #include <clock_control.h> #include <sections.h> #include <clock_control/stm32_clock_control.h> #include "uart_stm32.h" /* convenience defines */ #define DEV_CFG(dev) \ ((const struct uart_stm32_config * const)(dev)->config->config_info) #define DEV_DATA(dev) \ ((struct uart_stm32_data * const)(dev)->driver_data) #define UART_STRUCT(dev) \ ((USART_TypeDef *)(DEV_CFG(dev))->uconf.base) #define TIMEOUT 1000 static int uart_stm32_poll_in(struct device *dev, unsigned char *c) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; if (HAL_UART_Receive(UartHandle, (u8_t *)c, 1, TIMEOUT) == HAL_OK) { return 0; } else { return -1; } } static unsigned char uart_stm32_poll_out(struct device *dev, unsigned char c) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; HAL_UART_Transmit(UartHandle, (u8_t *)&c, 1, TIMEOUT); return c; } static inline void __uart_stm32_get_clock(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); __ASSERT_NO_MSG(clk); data->clock = clk; } #ifdef CONFIG_UART_INTERRUPT_DRIVEN static int uart_stm32_fifo_fill(struct device *dev, const u8_t *tx_data, int size) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; u8_t num_tx = 0; while ((size - num_tx > 0) && __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE)) { /* TXE flag will be cleared with byte write to DR register */ /* Send a character (8bit , parity none) */ #if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X) /* Use direct access for F1, F4 until Low Level API is available * Once it is we can remove the if/else */ UartHandle->Instance->DR = (tx_data[num_tx++] & (u8_t)0x00FF); #else LL_USART_TransmitData8(UartHandle->Instance, tx_data[num_tx++]); #endif } return num_tx; } static int uart_stm32_fifo_read(struct device *dev, u8_t *rx_data, const int size) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; u8_t num_rx = 0; while ((size - num_rx > 0) && __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_RXNE)) { /* Clear the interrupt */ __HAL_UART_CLEAR_FLAG(UartHandle, UART_FLAG_RXNE); /* Receive a character (8bit , parity none) */ #if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X) /* Use direct access for F1, F4 until Low Level API is available * Once it is we can remove the if/else */ rx_data[num_rx++] = (u8_t)(UartHandle->Instance->DR & (u8_t)0x00FF); #else rx_data[num_rx++] = LL_USART_ReceiveData8(UartHandle->Instance); #endif } return num_rx; } static void uart_stm32_irq_tx_enable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; __HAL_UART_ENABLE_IT(UartHandle, UART_IT_TC); } static void uart_stm32_irq_tx_disable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; __HAL_UART_DISABLE_IT(UartHandle, UART_IT_TC); } static int uart_stm32_irq_tx_ready(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE); } static int uart_stm32_irq_tx_complete(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE); } static void uart_stm32_irq_rx_enable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; __HAL_UART_ENABLE_IT(UartHandle, UART_IT_RXNE); } static void uart_stm32_irq_rx_disable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; __HAL_UART_DISABLE_IT(UartHandle, UART_IT_RXNE); } static int uart_stm32_irq_rx_ready(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_RXNE); } static void uart_stm32_irq_err_enable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; /* Enable FE, ORE interruptions */ __HAL_UART_ENABLE_IT(UartHandle, UART_IT_ERR); /* Enable Line break detection */ __HAL_UART_ENABLE_IT(UartHandle, UART_IT_LBD); /* Enable parity error interruption */ __HAL_UART_ENABLE_IT(UartHandle, UART_IT_PE); } static void uart_stm32_irq_err_disable(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; /* Disable FE, ORE interruptions */ __HAL_UART_DISABLE_IT(UartHandle, UART_IT_ERR); /* Disable Line break detection */ __HAL_UART_DISABLE_IT(UartHandle, UART_IT_LBD); /* Disable parity error interruption */ __HAL_UART_DISABLE_IT(UartHandle, UART_IT_PE); } static int uart_stm32_irq_is_pending(struct device *dev) { struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE | UART_FLAG_RXNE); } static int uart_stm32_irq_update(struct device *dev) { return 1; } static void uart_stm32_irq_callback_set(struct device *dev, uart_irq_callback_t cb) { struct uart_stm32_data *data = DEV_DATA(dev); data->user_cb = cb; } static void uart_stm32_isr(void *arg) { struct device *dev = arg; struct uart_stm32_data *data = DEV_DATA(dev); if (data->user_cb) { data->user_cb(dev); } } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ static const struct uart_driver_api uart_stm32_driver_api = { .poll_in = uart_stm32_poll_in, .poll_out = uart_stm32_poll_out, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .fifo_fill = uart_stm32_fifo_fill, .fifo_read = uart_stm32_fifo_read, .irq_tx_enable = uart_stm32_irq_tx_enable, .irq_tx_disable = uart_stm32_irq_tx_disable, .irq_tx_ready = uart_stm32_irq_tx_ready, .irq_tx_complete = uart_stm32_irq_tx_complete, .irq_rx_enable = uart_stm32_irq_rx_enable, .irq_rx_disable = uart_stm32_irq_rx_disable, .irq_rx_ready = uart_stm32_irq_rx_ready, .irq_err_enable = uart_stm32_irq_err_enable, .irq_err_disable = uart_stm32_irq_err_disable, .irq_is_pending = uart_stm32_irq_is_pending, .irq_update = uart_stm32_irq_update, .irq_callback_set = uart_stm32_irq_callback_set, #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ }; /** * @brief Initialize UART channel * * This routine is called to reset the chip in a quiescent state. * It is assumed that this function is called only once per UART. * * @param dev UART device struct * * @return 0 */ static int uart_stm32_init(struct device *dev) { const struct uart_stm32_config *config = DEV_CFG(dev); struct uart_stm32_data *data = DEV_DATA(dev); UART_HandleTypeDef *UartHandle = &data->huart; __uart_stm32_get_clock(dev); /* enable clock */ #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE clock_control_on(data->clock, (clock_control_subsys_t *)&config->pclken); #else clock_control_on(data->clock, config->clock_subsys); #endif UartHandle->Instance = UART_STRUCT(dev); UartHandle->Init.WordLength = UART_WORDLENGTH_8B; UartHandle->Init.StopBits = UART_STOPBITS_1; UartHandle->Init.Parity = UART_PARITY_NONE; UartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE; UartHandle->Init.Mode = UART_MODE_TX_RX; UartHandle->Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(UartHandle); #ifdef CONFIG_UART_INTERRUPT_DRIVEN config->uconf.irq_config_func(dev); #endif return 0; } /* Define clocks */ #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE #define STM32_CLOCK_UART(type, apb, n) \ .pclken = { .bus = STM32_CLOCK_BUS_ ## apb, \ .enr = LL_##apb##_GRP1_PERIPH_##type##n } #else #define STM32_CLOCK_UART(type, apb, n) \ .clock_subsys = UINT_TO_POINTER( \ STM32F10X_CLOCK_SUBSYS_##type##n) #endif /* CLOCK_CONTROL_STM32_CUBE */ #ifdef CONFIG_UART_INTERRUPT_DRIVEN #define STM32_UART_IRQ_HANDLER_DECL(n) \ static void uart_stm32_irq_config_func_##n(struct device *dev) #define STM32_UART_IRQ_HANDLER_FUNC(n) \ .irq_config_func = uart_stm32_irq_config_func_##n, #define STM32_UART_IRQ_HANDLER(n) \ static void uart_stm32_irq_config_func_##n(struct device *dev) \ { \ IRQ_CONNECT(PORT_ ## n ## _IRQ, \ CONFIG_UART_STM32_PORT_ ## n ## _IRQ_PRI, \ uart_stm32_isr, DEVICE_GET(uart_stm32_ ## n), \ 0); \ irq_enable(PORT_ ## n ## _IRQ); \ } #else #define STM32_UART_IRQ_HANDLER_DECL(n) #define STM32_UART_IRQ_HANDLER_FUNC(n) #define STM32_UART_IRQ_HANDLER(n) #endif #define UART_DEVICE_INIT_STM32(type, n, apb) \ STM32_UART_IRQ_HANDLER_DECL(n); \ \ static const struct uart_stm32_config uart_stm32_dev_cfg_##n = { \ .uconf = { \ .base = (u8_t *)CONFIG_UART_STM32_PORT_ ## n ## _BASE_ADDRESS, \ STM32_UART_IRQ_HANDLER_FUNC(n) \ }, \ STM32_CLOCK_UART(type, apb, n), \ }; \ \ static struct uart_stm32_data uart_stm32_dev_data_##n = { \ .huart = { \ .Init = { \ .BaudRate = CONFIG_UART_STM32_PORT_##n##_BAUD_RATE \ } \ } \ }; \ \ DEVICE_AND_API_INIT(uart_stm32_##n, CONFIG_UART_STM32_PORT_##n##_NAME, \ &uart_stm32_init, \ &uart_stm32_dev_data_##n, &uart_stm32_dev_cfg_##n, \ PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ &uart_stm32_driver_api); \ \ STM32_UART_IRQ_HANDLER(n) #ifdef CONFIG_UART_STM32_PORT_1 UART_DEVICE_INIT_STM32(USART, 1, APB2) #endif /* CONFIG_UART_STM32_PORT_1 */ #ifdef CONFIG_UART_STM32_PORT_2 UART_DEVICE_INIT_STM32(USART, 2, APB1) #endif /* CONFIG_UART_STM32_PORT_2 */ #ifdef CONFIG_UART_STM32_PORT_3 UART_DEVICE_INIT_STM32(USART, 3, APB1) #endif /* CONFIG_UART_STM32_PORT_3 */ #ifdef CONFIG_UART_STM32_PORT_4 UART_DEVICE_INIT_STM32(UART, 4, APB1) #endif /* CONFIG_UART_STM32_PORT_4 */ #ifdef CONFIG_UART_STM32_PORT_5 UART_DEVICE_INIT_STM32(UART, 5, APB1) #endif /* CONFIG_UART_STM32_PORT_5 */ #ifdef CONFIG_UART_STM32_PORT_6 UART_DEVICE_INIT_STM32(USART, 6, APB2) #endif /* CONFIG_UART_STM32_PORT_6 */ #ifdef CONFIG_UART_STM32_PORT_7 UART_DEVICE_INIT_STM32(UART, 7, APB1) #endif /* CONFIG_UART_STM32_PORT_7 */ #ifdef CONFIG_UART_STM32_PORT_8 UART_DEVICE_INIT_STM32(UART, 8, APB1) #endif /* CONFIG_UART_STM32_PORT_8 */ #ifdef CONFIG_UART_STM32_PORT_9 UART_DEVICE_INIT_STM32(UART, 9, APB2) #endif /* CONFIG_UART_STM32_PORT_9 */ #ifdef CONFIG_UART_STM32_PORT_10 UART_DEVICE_INIT_STM32(UART, 10, APB2) #endif /* CONFIG_UART_STM32_PORT_10 */ |