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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 | /* * Copyright (c) 2017, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of the Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL CORPORATION OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include "power_states.h" #include "vreg.h" #if (QM_SENSOR) #include "qm_sensor_regs.h" #endif #include "soc_watch.h" void qm_power_soc_sleep() { /* Go to sleep */ QM_SCSS_PMU->slp_cfg &= ~QM_SCSS_SLP_CFG_LPMODE_EN; SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_SLP_CFG); SOC_WATCH_LOG_EVENT(SOCW_EVENT_SLEEP, 0); QM_SCSS_PMU->pm1c |= QM_SCSS_PM1C_SLPEN; } void qm_power_soc_deep_sleep() { /* Switch to linear regulators. * For low power deep sleep mode, it is a requirement that the platform * voltage regulators are not in switching mode. */ vreg_plat1p8_set_mode(VREG_MODE_LINEAR); vreg_plat3p3_set_mode(VREG_MODE_LINEAR); /* Enable low power sleep mode */ QM_SCSS_PMU->slp_cfg |= QM_SCSS_SLP_CFG_LPMODE_EN; SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_SLP_CFG); SOC_WATCH_LOG_EVENT(SOCW_EVENT_SLEEP, 0); QM_SCSS_PMU->pm1c |= QM_SCSS_PM1C_SLPEN; } #if (ENABLE_RESTORE_CONTEXT) && (!QM_SENSOR) /* * The restore trap address is stored in the variable __x86_restore_info. * The variable __x86_restore_info is defined in the linker script as a new * and independent memory segment. */ extern uint32_t *__x86_restore_info; /* * The stack pointer is saved in the global variable sp_restore_storage * by qm_x86_save_context() before sleep and it is restored by * qm_x86_restore_context() after wake up. */ uint32_t sp_restore_storage; void qm_power_soc_sleep_restore() { /* * Save x86 restore trap address. * The first parameter in this macro represents the label defined in * the qm_x86_restore_context() macro, which is actually the restore * trap address. */ qm_x86_set_resume_vector(sleep_restore_trap, __x86_restore_info); /* Save x86 execution context. */ qm_x86_save_context(sp_restore_storage); /* Set restore flags. */ qm_power_soc_set_x86_restore_flag(); /* Enter sleep. */ qm_power_soc_sleep(); /* * Restore x86 execution context. * The bootloader code will jump to this location after waking up from * sleep. The restore trap address is the label defined in the macro. * That label is exposed here through the first parameter. */ qm_x86_restore_context(sleep_restore_trap, sp_restore_storage); } void qm_power_soc_deep_sleep_restore() { /* * Save x86 restore trap address. * The first parameter in this macro represents the label defined in * the qm_x86_restore_context() macro, which is actually the restore * trap address. */ qm_x86_set_resume_vector(deep_sleep_restore_trap, __x86_restore_info); /* Save x86 execution context. */ qm_x86_save_context(sp_restore_storage); /* Set restore flags. */ qm_power_soc_set_x86_restore_flag(); /* Enter sleep. */ qm_power_soc_deep_sleep(); /* * Restore x86 execution context. * The bootloader code will jump to this location after waking up from * sleep. The restore trap address is the label defined in the macro. * That label is exposed here through the first parameter. */ qm_x86_restore_context(deep_sleep_restore_trap, sp_restore_storage); } void qm_power_sleep_wait() { /* * Save x86 restore trap address. * The first parameter in this macro represents the label defined in * the qm_x86_restore_context() macro, which is actually the restore * trap address. */ qm_x86_set_resume_vector(sleep_restore_trap, __x86_restore_info); /* Save x86 execution context. */ qm_x86_save_context(sp_restore_storage); /* Set restore flags. */ qm_power_soc_set_x86_restore_flag(); /* Enter C2 and stay in it until sleep and wake-up. */ while (1) { qm_power_cpu_c2(); } /* * Restore x86 execution context. * The bootloader code will jump to this location after waking up from * sleep. The restore trap address is the label defined in the macro. * That label is exposed here through the first parameter. */ qm_x86_restore_context(sleep_restore_trap, sp_restore_storage); } void qm_power_soc_set_x86_restore_flag(void) { QM_SCSS_GP->gps0 |= BIT(QM_GPS0_BIT_X86_WAKEUP); } #endif /* ENABLE_RESTORE_CONTEXT */ #if (!QM_SENSOR) void qm_power_cpu_c1() { SOC_WATCH_LOG_EVENT(SOCW_EVENT_HALT, 0); /* * STI sets the IF flag. After the IF flag is set, * the core begins responding to external, * maskable interrupts after the next instruction is executed. * When this function is called with interrupts disabled, * this guarantees that an interrupt is caught only * after the processor has transitioned into HLT. */ __asm__ __volatile__("sti\n\t" "hlt\n\t"); } void qm_power_cpu_c2() { QM_SCSS_CCU->ccu_lp_clk_ctl &= ~QM_SCSS_CCU_C2_LP_EN; SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_LP_CLK_CTL); /* Read P_LVL2 to trigger a C2 request */ SOC_WATCH_LOG_EVENT(SOCW_EVENT_SLEEP, 0); QM_SCSS_PMU->p_lvl2; } void qm_power_cpu_c2lp() { QM_SCSS_CCU->ccu_lp_clk_ctl |= QM_SCSS_CCU_C2_LP_EN; SOC_WATCH_LOG_EVENT(SOCW_EVENT_REGISTER, SOCW_REG_CCU_LP_CLK_CTL); /* Read P_LVL2 to trigger a C2 request */ SOC_WATCH_LOG_EVENT(SOCW_EVENT_SLEEP, 0); QM_SCSS_PMU->p_lvl2; } #endif |