Boot Linux faster!

Check our new training course

Boot Linux faster!

Check our new training course
and Creative Commons CC-BY-SA
lecture and lab materials

Bootlin logo

Elixir Cross Referencer

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
/*
 * Copyright (c) 2016 Linaro Limited.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <kernel.h>

#include <device.h>
#include <errno.h>
#include <gpio.h>
#include <init.h>
#include <soc.h>
#include <clock_control/arm_clock_control.h>

#include "gpio_cmsdk_ahb.h"
#include "gpio_utils.h"

/**
 * @brief GPIO driver for ARM CMSDK AHB GPIO
 */

typedef void (*gpio_config_func_t)(struct device *port);

struct gpio_cmsdk_ahb_cfg {
	volatile struct gpio_cmsdk_ahb *port;
	gpio_config_func_t gpio_config_func;
	/* GPIO Clock control in Active State */
	struct arm_clock_control_t gpio_cc_as;
	/* GPIO Clock control in Sleep State */
	struct arm_clock_control_t gpio_cc_ss;
	/* GPIO Clock control in Deep Sleep State */
	struct arm_clock_control_t gpio_cc_dss;
};

struct gpio_cmsdk_ahb_dev_data {
	/* list of callbacks */
	sys_slist_t gpio_cb;
};

static void cmsdk_ahb_gpio_config(struct device *dev, uint32_t mask, int flags)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;

	/* Disable the pin and return as setup is meaningless now */
	if (flags & GPIO_PIN_DISABLE) {
		cfg->port->altfuncset = mask;
		return;
	}

	/*
	 * Setup the pin direction
	 * Output Enable:
	 * 0 - Input
	 * 1 - Output
	 */
	if ((flags & GPIO_DIR_MASK) == GPIO_DIR_OUT) {
		cfg->port->outenableset = mask;
	} else {
		cfg->port->outenableclr = mask;
	}

	/* Setup interrupt config */
	if (flags & GPIO_INT) {
		if (flags & GPIO_INT_DOUBLE_EDGE) {
			/* FIXME: Not supported in this iteration */
		} else {
			/*
			 * Interrupt type:
			 * 0 - LOW or HIGH level
			 * 1 - For falling or rising
			 */
			if (flags & GPIO_INT_EDGE) {
				cfg->port->inttypeclr = mask;
			} else {
				cfg->port->inttypeset = mask;
			}
			/*
			 * Interrupt polarity:
			 * 0 - Low level or falling edge
			 * 1 - High level or rising edge
			 */
			if (flags & GPIO_INT_ACTIVE_HIGH) {
				cfg->port->intpolset = mask;
			} else {
				cfg->port->intpolclr = mask;
			}
		}
	}

	/* Enable the pin last after pin setup */
	if (flags & GPIO_PIN_ENABLE) {
		cfg->port->altfuncclr = mask;
	}
}

/**
 * @brief Configure pin or port
 *
 * @param dev Device struct
 * @param access_op Access operation (pin or port)
 * @param pin The pin number
 * @param flags Flags of pin or port
 *
 * @return 0 if successful, failed otherwise
 */
static int gpio_cmsdk_ahb_config(struct device *dev, int access_op,
				 uint32_t pin, int flags)
{
	switch (access_op) {
	case GPIO_ACCESS_BY_PIN:
		cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
		break;
	case GPIO_ACCESS_BY_PORT:
		cmsdk_ahb_gpio_config(dev, (0xFFFF), flags);
		break;
	default:
		return -ENOTSUP;
	}

	return 0;
}

/**
 * @brief Set the pin or port output
 *
 * @param dev Device struct
 * @param access_op Access operation (pin or port)
 * @param pin The pin number
 * @param value Value to set (0 or 1)
 *
 * @return 0 if successful, failed otherwise
 */
static int gpio_cmsdk_ahb_write(struct device *dev, int access_op,
				uint32_t pin, uint32_t value)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
	uint32_t key;

	switch (access_op) {
	case GPIO_ACCESS_BY_PIN:
		if (value) {
			/*
			 * The irq_lock() here is required to prevent concurrent
			 * callers to corrupt the pin states.
			 */
			key = irq_lock();
			/* set the pin */
			cfg->port->dataout |= BIT(pin);
			irq_unlock(key);
		} else {
			/*
			 * The irq_lock() here is required to prevent concurrent
			 * callers to corrupt the pin states.
			 */
			key = irq_lock();
			/* clear the pin */
			cfg->port->dataout &= ~(BIT(pin));
			irq_unlock(key);
		}
		break;
	case GPIO_ACCESS_BY_PORT:
		if (value) {
			/* set all pins */
			cfg->port->dataout = 0xFFFF;
		} else {
			/* clear all pins */
			cfg->port->dataout = 0x0;
		}
		break;
	default:
		return -ENOTSUP;
	}

	return 0;
}

/**
 * @brief Read the pin or port status
 *
 * @param dev Device struct
 * @param access_op Access operation (pin or port)
 * @param pin The pin number
 * @param value Value of input pin(s)
 *
 * @return 0 if successful, failed otherwise
 */
static int gpio_cmsdk_ahb_read(struct device *dev, int access_op,
			       uint32_t pin, uint32_t *value)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;

	*value = cfg->port->data;

	switch (access_op) {
	case GPIO_ACCESS_BY_PIN:
		*value = (*value >> pin) & 0x1;
		break;
	case GPIO_ACCESS_BY_PORT:
		break;
	default:
		return -ENOTSUP;
	}

	return 0;
}

static void gpio_cmsdk_ahb_isr(void *arg)
{
	struct device *dev = (struct device *)arg;
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
	struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;
	uint32_t int_stat;

	int_stat = cfg->port->intstatus;

	_gpio_fire_callbacks(&data->gpio_cb, dev, int_stat);

	/* clear the port interrupts */
	cfg->port->intclear = 0xFFFFFFFF;
}

static int gpio_cmsdk_ahb_manage_callback(struct device *dev,
					  struct gpio_callback *callback,
					  bool set)
{
	struct gpio_cmsdk_ahb_dev_data *data = dev->driver_data;

	_gpio_manage_callback(&data->gpio_cb, callback, set);

	return 0;
}

static int gpio_cmsdk_ahb_enable_callback(struct device *dev,
					  int access_op, uint32_t pin)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
	uint32_t mask;

	switch (access_op) {
	case GPIO_ACCESS_BY_PIN:
		mask = BIT(pin);
		break;
	case GPIO_ACCESS_BY_PORT:
		mask = 0xFFFF;
		break;
	default:
		return -ENOTSUP;
	}

	cfg->port->intenset |= mask;

	return 0;
}

static int gpio_cmsdk_ahb_disable_callback(struct device *dev,
					   int access_op, uint32_t pin)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;
	uint32_t mask;

	switch (access_op) {
	case GPIO_ACCESS_BY_PIN:
		mask = BIT(pin);
		break;
	case GPIO_ACCESS_BY_PORT:
		mask = 0xFFFF;
		break;
	default:
		return -ENOTSUP;
	}

	cfg->port->intenclr |= mask;

	return 0;
}

static const struct gpio_driver_api gpio_cmsdk_ahb_drv_api_funcs = {
	.config = gpio_cmsdk_ahb_config,
	.write = gpio_cmsdk_ahb_write,
	.read = gpio_cmsdk_ahb_read,
	.manage_callback = gpio_cmsdk_ahb_manage_callback,
	.enable_callback = gpio_cmsdk_ahb_enable_callback,
	.disable_callback = gpio_cmsdk_ahb_disable_callback,
};

/**
 * @brief Initialization function of GPIO
 *
 * @param dev Device struct
 * @return 0 if successful, failed otherwise.
 */
static int gpio_cmsdk_ahb_init(struct device *dev)
{
	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config->config_info;

#ifdef CONFIG_CLOCK_CONTROL
	/* Enable clock for subsystem */
	struct device *clk =
		device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);

#ifdef CONFIG_SOC_SERIES_BEETLE
	clock_control_on(clk, (clock_control_subsys_t *) &cfg->gpio_cc_as);
	clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_ss);
	clock_control_off(clk, (clock_control_subsys_t *) &cfg->gpio_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#endif /* CONFIG_CLOCK_CONTROL */

	cfg->gpio_config_func(dev);

	return 0;
}

/* Port 0 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT0
static void gpio_cmsdk_ahb_config_0(struct device *dev);

static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = {
	.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0),
	.gpio_config_func = gpio_cmsdk_ahb_config_0,
	.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
		       .device = CMSDK_AHB_GPIO0,},
	.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
		       .device = CMSDK_AHB_GPIO0,},
	.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
			.device = CMSDK_AHB_GPIO0,},
};

static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data;

DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0,
		    CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME,
		    gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_0_data,
		    &gpio_cmsdk_ahb_0_cfg, POST_KERNEL,
		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
		    &gpio_cmsdk_ahb_drv_api_funcs);

static void gpio_cmsdk_ahb_config_0(struct device *dev)
{
	IRQ_CONNECT(IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI,
		    gpio_cmsdk_ahb_isr,
		    DEVICE_GET(gpio_cmsdk_ahb_0), 0);
	irq_enable(IRQ_PORT0_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */

/* Port 1 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT1
static void gpio_cmsdk_ahb_config_1(struct device *dev);

static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = {
	.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1),
	.gpio_config_func = gpio_cmsdk_ahb_config_1,
	.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
		       .device = CMSDK_AHB_GPIO1,},
	.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
		       .device = CMSDK_AHB_GPIO1,},
	.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
			.device = CMSDK_AHB_GPIO1,},
};

static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data;

DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1,
		    CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME,
		    gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_1_data,
		    &gpio_cmsdk_ahb_1_cfg, POST_KERNEL,
		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
		    &gpio_cmsdk_ahb_drv_api_funcs);

static void gpio_cmsdk_ahb_config_1(struct device *dev)
{
	IRQ_CONNECT(IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI,
		    gpio_cmsdk_ahb_isr,
		    DEVICE_GET(gpio_cmsdk_ahb_1), 0);
	irq_enable(IRQ_PORT1_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */

/* Port 2 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT2
static void gpio_cmsdk_ahb_config_2(struct device *dev);

static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = {
	.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2),
	.gpio_config_func = gpio_cmsdk_ahb_config_2,
	.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
		       .device = CMSDK_AHB_GPIO2,},
	.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
		       .device = CMSDK_AHB_GPIO2,},
	.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
			.device = CMSDK_AHB_GPIO2,},
};

static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data;

DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2,
		    CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME,
		    gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_2_data,
		    &gpio_cmsdk_ahb_2_cfg, POST_KERNEL,
		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
		    &gpio_cmsdk_ahb_drv_api_funcs);

static void gpio_cmsdk_ahb_config_2(struct device *dev)
{
	IRQ_CONNECT(IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI,
		    gpio_cmsdk_ahb_isr,
		    DEVICE_GET(gpio_cmsdk_ahb_2), 0);
	irq_enable(IRQ_PORT2_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */

/* Port 3 */
#ifdef CONFIG_GPIO_CMSDK_AHB_PORT3
static void gpio_cmsdk_ahb_config_3(struct device *dev);

static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = {
	.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3),
	.gpio_config_func = gpio_cmsdk_ahb_config_3,
	.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
		       .device = CMSDK_AHB_GPIO3,},
	.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
		       .device = CMSDK_AHB_GPIO3,},
	.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
			.device = CMSDK_AHB_GPIO3,},
};

static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data;

DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3,
		    CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME,
		    gpio_cmsdk_ahb_init, &gpio_cmsdk_ahb_3_data,
		    &gpio_cmsdk_ahb_3_cfg, POST_KERNEL,
		    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
		    &gpio_cmsdk_ahb_drv_api_funcs);

static void gpio_cmsdk_ahb_config_3(struct device *dev)
{
	IRQ_CONNECT(IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI,
		    gpio_cmsdk_ahb_isr,
		    DEVICE_GET(gpio_cmsdk_ahb_3), 0);
	irq_enable(IRQ_PORT3_ALL);
}
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */