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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 | # # Copyright (c) 2014 Wind River Systems, Inc. # Copyright (c) 2016 Synopsys, Inc. All rights reserved. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # if SOC_EM7D config SOC default em7d config NUM_IRQ_PRIO_LEVELS # This processor supports 4 priority levels: # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). # TODO: But regular irq nesting is not implemented -- # so this must be 2 for now. default 2 config NUM_IRQS # must be > the highest interrupt number used default 36 config RGF_NUM_BANKS default 1 config SYS_CLOCK_HW_CYCLES_PER_SEC default 30000000 config HARVARD def_bool n config FLASH_BASE_ADDRESS default 0x00000000 config FLASH_SIZE default 0 # em7d has no FLASH so size is 0. config SRAM_BASE_ADDRESS default 0x10000000 config SRAM_SIZE default 131072 config ICCM_BASE_ADDRESS default 0x00000000 config ICCM_SIZE default 256 config DCCM_BASE_ADDRESS default 0x80000000 config DCCM_SIZE default 128 config CACHE_FLUSHING def_bool y if GPIO config GPIO_DW def_bool y if GPIO_DW config GPIO_DW_0 def_bool y if GPIO_DW_0 config GPIO_DW_0_NAME default "GPIO_PORTA" config GPIO_DW_0_IRQ_PRI default 1 endif # GPIO_DW_0 config GPIO_DW_1 def_bool y if GPIO_DW_1 config GPIO_DW_1_NAME default "GPIO_PORTB" config GPIO_DW_1_IRQ_PRI default 1 endif # GPIO_DW_1 config GPIO_DW_2 def_bool y if GPIO_DW_2 config GPIO_DW_2_IRQ_PRI default 1 config GPIO_DW_2_NAME default "GPIO_PORTC" endif # GPIO_DW_2 config GPIO_DW_3 def_bool y if GPIO_DW_3 config GPIO_DW_3_IRQ_PRI default 1 config GPIO_DW_3_NAME default "GPIO_PORTD" endif # GPIO_DW_3 endif # GPIO_DW endif # GPIO if I2C config I2C_CLOCK_SPEED default 100 config I2C_DW def_bool y if I2C_DW config I2C_0 def_bool y if I2C_0 config I2C_0_NAME default "I2C_0" config I2C_0_DEFAULT_CFG default 0x3 config I2C_0_IRQ_PRI default 1 endif # I2C_0 config I2C_1 def_bool y if I2C_1 config I2C_1_NAME default "I2C_1" config I2C_1_DEFAULT_CFG default 0x3 config I2C_1_IRQ_PRI default 1 endif # I2C_1 endif # I2C_DW endif # I2C if UART_NS16550 config UART_NS16550_PORT_0 def_bool n if UART_NS16550_PORT_0 config UART_NS16550_PORT_0_NAME default "UART_0" config UART_NS16550_PORT_0_IRQ_PRI default 1 config UART_NS16550_PORT_0_BAUD_RATE default 115200 config UART_NS16550_PORT_0_OPTIONS default 0 endif # UART_NS16550_PORT_0 config UART_NS16550_PORT_1 def_bool y if UART_NS16550_PORT_1 config UART_NS16550_PORT_1_NAME default "UART_1" config UART_NS16550_PORT_1_IRQ_PRI default 1 config UART_NS16550_PORT_1_BAUD_RATE default 115200 config UART_NS16550_PORT_1_OPTIONS default 0 endif # UART_NS16550_PORT_1 endif # UART_NS16550 if UART_CONSOLE config UART_CONSOLE_ON_DEV_NAME default "UART_1" endif if SPI config SPI_DW def_bool y if SPI_DW config SPI_DW_CLOCK_GATE def_bool n config SPI_DW_FIFO_DEPTH default 32 config SPI_DW_ARC_AUX_REGS def_bool n config SPI_0 def_bool y if SPI_0 config SPI_0_IRQ_PRI default 0 endif # SPI_0 config SPI_1 def_bool y if SPI_1 config SPI_1_IRQ_PRI default 0 endif # SPI_1 endif # SPI_DW endif # SPI endif #SOC_EM7D |