# Kconfig - x86 general configuration options
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prompt "x86 SoC Selection"
depends on X86
menu "x86 Options"
depends on X86
# Hidden CPU family configs which are to be selected by
# individual SoC.
This option signifies the use of a CPU from the Atom family.
This option signifies the use of a CPU from the Minute IA family.
# End hidden CPU family configs
# Hidden config selected by CPU family
This option is enabled when the CPU has hardware floating point
menu "Processor Capabilities"
prompt "IAMCU calling convention"
The IAMCU calling convention changes the X86 C calling convention to
pass some arguments via registers allowing for code size and performance
improvements. Great care needs to be taken if you have assembly code
that will be called from C or C code called from assembly code, the
assembly code will need to be updated to conform to the new calling
convention. If in doubt say N
menu "Floating Point Options"
depends on CPU_HAS_FPU
prompt "Floating point registers"
This option allows threads to use the x87 FPU/MMX registers. The
registers may be used by any number of cooperative threads or by
a single preemptible thread, but not both, since the kernel does not
preserve FPU context information when switching between threads.
Additional options must be enabled to permit the use of SSE registers or
to permit floating point register use by multiple preemptible threads.
Disabling this option means that any thread that uses the floating
point registers will get a fatal exception.
prompt "Floating point register sharing"
depends on FLOAT
This option allows multiple preemptible threads to use the floating
point registers. Any preemptible thread that uses the registers must
provide stack space where the kernel can save FPU context info during
a preemptive context switch. A thread that uses only the x87 FPU/MMX
registers must provide 108 bytes of added stack space, while a thread
the uses the SSE registers must provide 464 bytes of added stack space.
prompt "SSE registers"
depends on FLOAT
This option enables the use of SSE registers by threads.
prompt "Compiler-generated SSEx instructions"
depends on SSE
This option allows the compiler to generate SSEx instructions for
performing floating point math. This can greatly improve performance
when exactly the same operations are to be performed on multiple
data objects; however, it can also significantly reduce performance
when pre-emptive task switches occur because of the larger register
set that must be saved and restored.
Disabling this option means that the compiler utilizes only the
x87 instruction set for floating point operations.
prompt "Reboot implementation"
depends on REBOOT
prompt "Reboot via RST_CNT register"
Reboot via the RST_CNT register, going back to BIOS.
This option signifies the use of a CPU based on the Intel IA-32
instruction set architecture.
prompt "Support IA32 legacy IO ports"
depends on ISA_IA32
This option enables IA32 legacy IO ports. Note these are much slower
than memory access, so they should be used in last resort.
This option signifies the use of an Intel CPU that supports
the CMOV instruction.
prompt "Detect cache line size at runtime"
This option enables querying the CPUID register for finding the cache line
size at the expense of taking more memory and code and a slightly increased
If the CPU's cache line size is known in advance, disable this option and
manually enter the value for CACHE_LINE_SIZE.
prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
default 0 if CACHE_LINE_SIZE_DETECT
default 64 if CPU_ATOM
Size in bytes of a CPU cache line.
Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.
prompt "CLFLUSH instruction supported"
depends on !CLFLUSH_DETECT && CACHE_FLUSHING
An implementation of sys_cache_flush() that uses CLFLUSH is made
available, instead of the one using WBINVD.
This option should only be enabled if it is known in advance that the
CPU supports the CLFLUSH instruction. It disables runtime detection of
CLFLUSH support thereby reducing both memory footprint and boot time.
prompt "Detect support of CLFLUSH instruction at runtime"
depends on CACHE_FLUSHING
This option should be enabled if it is not known in advance whether the
CPU supports the CLFLUSH instruction or not.
The CPU is queried at boot time to determine which of the multiple
implementations of sys_cache_flush() linked into the image is the
correct one to use.
If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.
depends on CLFLUSH_DETECT
prompt "Enable cache flushing mechanism"
This links in the sys_cache_flush() function. A mechanism for flushing the
cache must be selected as well. By default, that mechanism is discovered at
menu "Board Capabilities"
bool "Disable PIC"
This option disables all interrupts on the PIC
bool "Enable IRQ offload"
Enable irq_offload() API which allows functions to be synchronously
run in interrupt context. Uses one entry in the IDT. Mainly useful
for test cases.
int "IDT vector to use for IRQ offload"
default 63 if MVIC
default 32 if !MVIC
range 32 255
depends on IRQ_OFFLOAD
Specify the IDT vector to use for the IRQ offload interrupt handler.
The default should be fine for most arches, but on systems like MVIC
where there is a fixed IRQ-to-vector mapping another value may be
needed to avoid collision.
Specify whether the current interrupt controller in use has a fixed
mapping between IDT vectors and IRQ lines.