Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 | /*
* Copyright (c) 2012-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Intel HPET device driver
*
* This module implements a kernel device driver for the Intel High Precision
* Event Timer (HPET) device, and provides the standard "system clock driver"
* interfaces.
*
* The driver utilizes HPET timer0 to provide kernel ticks.
*
* \INTERNAL IMPLEMENTATION DETAILS
* The HPET device driver makes no assumption about the initial state of the
* HPET, and explicitly puts the device into a reset-like state. It also assumes
* that the main up counter never wraps around to 0 during the lifetime of the
* system.
*
* The platform can configure the HPET to use level rather than the default edge
* sensitive interrupts by enabling the following configuration parameters:
* CONFIG_HPET_TIMER_LEVEL_HIGH or CONFIG_HPET_TIMER_LEVEL_LOW
*
* When not configured to support tickless idle timer0 is programmed in periodic
* mode so it automatically generates a single interrupt per kernel tick
* interval.
*
* When configured to support tickless idle timer0 is programmed in one-shot
* mode. When the CPU is not idling the timer interrupt handler sets the timer
* to expire when the next kernel tick is due, waits for this to occur, and then
* repeats this "ad infinitum". When the CPU begins idling the timer driver
* reprograms the expiry time for the timer (thereby overriding the previously
* scheduled timer interrupt) and waits for the timer to expire or for a
* non-timer interrupt to occur. When the CPU ceases idling the driver
* determines how many complete ticks have elapsed, reprograms the timer so that
* it expires on the next tick, and announces the number of elapsed ticks (if
* any) to the microkernel.
*
* In a nanokernel-only system this device driver omits more complex
* capabilities (such as tickless idle support) that are only used with a
* microkernel.
*/
#include <nanokernel.h>
#include <toolchain.h>
#include <sections.h>
#include <sys_clock.h>
#include <drivers/ioapic.h>
#include <drivers/system_timer.h>
#include <nano_private.h>
#ifdef CONFIG_MICROKERNEL
#include <microkernel.h>
extern struct nano_stack _k_command_stack;
#endif /* CONFIG_MICROKERNEL */
#include <board.h>
/* HPET register offsets */
#define GENERAL_CAPS_REG 0 /* 64-bit register */
#define GENERAL_CONFIG_REG 0x10 /* 64-bit register */
#define GENERAL_INT_STATUS_REG 0x20 /* 64-bit register */
#define MAIN_COUNTER_VALUE_REG 0xf0 /* 64-bit register */
#define TIMER0_CONFIG_CAPS_REG 0x100 /* 64-bit register */
#define TIMER0_COMPARATOR_REG 0x108 /* 64-bit register */
#define TIMER0_FSB_INT_ROUTE_REG 0x110 /* 64-bit register */
/* read the GENERAL_CAPS_REG to determine # of timers actually implemented */
#define TIMER1_CONFIG_CAP_REG 0x120 /* 64-bit register */
#define TIMER1_COMPARATOR_REG 0x128 /* 64-bit register */
#define TIMER1_FSB_INT_ROUTE_REG 0x130 /* 64-bit register */
#define TIMER2_CONFIG_CAP_REG 0x140 /* 64-bit register */
#define TIMER2_COMPARATOR_REG 0x148 /* 64-bit register */
#define TIMER2_FSB_INT_ROUTE_REG 0x150 /* 64-bit register */
/* convenience macros for accessing specific HPET registers */
#define _HPET_GENERAL_CAPS ((volatile uint64_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_CAPS_REG))
/*
* Although the general configuration register is 64-bits, only a 32-bit access
* is performed since the most significant bits contain no useful information.
*/
#define _HPET_GENERAL_CONFIG ((volatile uint32_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_CONFIG_REG))
/*
* Although the general interrupt status is 64-bits, only a 32-bit access
* is performed since this driver only utilizes timer0
* (i.e. there is no need to determine the interrupt status of other timers).
*/
#define _HPET_GENERAL_INT_STATUS ((volatile uint32_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + GENERAL_INT_STATUS_REG))
#define _HPET_MAIN_COUNTER_VALUE ((volatile uint64_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
#define _HPET_MAIN_COUNTER_LSW ((volatile uint32_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG))
#define _HPET_MAIN_COUNTER_MSW ((volatile uint32_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + MAIN_COUNTER_VALUE_REG + 0x4))
#define _HPET_TIMER0_CONFIG_CAPS ((volatile uint64_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_CONFIG_CAPS_REG))
#define _HPET_TIMER0_COMPARATOR ((volatile uint64_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_COMPARATOR_REG))
#define _HPET_TIMER0_FSB_INT_ROUTE ((volatile uint64_t *) \
(CONFIG_HPET_TIMER_BASE_ADDRESS + TIMER0_FSB_INT_ROUTE_REG))
/* general capabilities register macros */
#define HPET_COUNTER_CLK_PERIOD(caps) (caps >> 32)
#define HPET_NUM_TIMERS(caps) (((caps >> 8) & 0x1f) + 1)
#define HPET_IS64BITS(caps) (caps & 0x1000)
/* general configuration register macros */
#define HPET_ENABLE_CNF (1 << 0)
#define HPET_LEGACY_RT_CNF (1 << 1)
/* timer N configuration and capabilities register macros */
#define HPET_Tn_INT_ROUTE_CAP(caps) (caps > 32)
#define HPET_Tn_FSB_INT_DEL_CAP(caps) (caps & (1 << 15))
#define HPET_Tn_FSB_EN_CNF (1 << 14)
#define HPET_Tn_INT_ROUTE_CNF_MASK (0x1f << 9)
#define HPET_Tn_INT_ROUTE_CNF_SHIFT 9
#define HPET_Tn_32MODE_CNF (1 << 8)
#define HPET_Tn_VAL_SET_CNF (1 << 6)
#define HPET_Tn_SIZE_CAP(caps) (caps & (1 << 5))
#define HPET_Tn_PER_INT_CAP(caps) (caps & (1 << 4))
#define HPET_Tn_TYPE_CNF (1 << 3)
#define HPET_Tn_INT_ENB_CNF (1 << 2)
#define HPET_Tn_INT_TYPE_CNF (1 << 1)
/*
* HPET comparator delay factor; this is the minimum value by which a new
* timer expiration setting must exceed the current main counter value when
* programming a timer in one-shot mode. Failure to allow for delays incurred
* in programming a timer may result in the HPET not generating an interrupt
* when the desired expiration time is reached. (See HPET documentation for
* a more complete description of this issue.)
*
* The value is expressed in main counter units. For example, if the HPET main
* counter increments at a rate of 19.2 MHz, this delay corresponds to 10 us
* (or about 0.1% of a system clock tick, assuming a tick rate of 100 Hz).
*/
#define HPET_COMP_DELAY 192
#if defined(CONFIG_HPET_TIMER_FALLING_EDGE)
#define HPET_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_LOW)
#elif defined(CONFIG_HPET_TIMER_RISING_EDGE)
#define HPET_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
#elif defined(CONFIG_HPET_TIMER_LEVEL_HIGH)
#define HPET_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH)
#elif defined(CONFIG_HPET_TIMER_LEVEL_LOW)
#define HPET_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
#endif
#ifdef CONFIG_INT_LATENCY_BENCHMARK
static uint32_t main_count_first_irq_value;
static uint32_t main_count_expected_value;
extern uint32_t _hw_irq_to_c_handler_latency;
#endif
#ifdef CONFIG_HPET_TIMER_DEBUG
#include <misc/printk.h>
#define PRINTK(...) printk(__VA_ARGS__)
#else
#define PRINTK(...)
#endif
#ifdef CONFIG_TICKLESS_IDLE
/* additional globals, locals, and forward declarations */
extern int32_t _sys_idle_elapsed_ticks;
/* main counter units per system tick */
static uint32_t __noinit counter_load_value;
/* counter value for most recent tick */
static uint64_t counter_last_value;
/* # ticks timer is programmed for */
static int32_t programmed_ticks = 1;
/* is stale interrupt possible? */
static int stale_irq_check;
/**
*
* @brief Safely read the main HPET up counter
*
* This routine simulates an atomic read of the 64-bit system clock on CPUs
* that only support 32-bit memory accesses. The most significant word
* of the counter is read twice to ensure it doesn't change while the least
* significant word is being retrieved (as per HPET documentation).
*
* @return current 64-bit counter value
*/
static uint64_t _hpetMainCounterAtomic(void)
{
uint32_t highBits;
uint32_t lowBits;
do {
highBits = *_HPET_MAIN_COUNTER_MSW;
lowBits = *_HPET_MAIN_COUNTER_LSW;
} while (highBits != *_HPET_MAIN_COUNTER_MSW);
return ((uint64_t)highBits << 32) | lowBits;
}
#endif /* CONFIG_TICKLESS_IDLE */
/**
*
* @brief System clock tick handler
*
* This routine handles the system clock tick interrupt. A TICK_EVENT event
* is pushed onto the microkernel stack.
*
* @return N/A
*/
void _timer_int_handler(void *unused)
{
ARG_UNUSED(unused);
#if defined(CONFIG_HPET_TIMER_LEVEL_LOW) || defined(CONFIG_HPET_TIMER_LEVEL_HIGH)
/* Acknowledge interrupt */
*_HPET_GENERAL_INT_STATUS = 1;
#endif
#ifdef CONFIG_INT_LATENCY_BENCHMARK
uint32_t delta = *_HPET_MAIN_COUNTER_VALUE - main_count_expected_value;
if (_hw_irq_to_c_handler_latency > delta) {
/* keep the lowest value observed */
_hw_irq_to_c_handler_latency = delta;
}
/* compute the next expected main counter value */
main_count_expected_value += main_count_first_irq_value;
#endif
#ifndef CONFIG_TICKLESS_IDLE
/*
* one more tick has occurred -- don't need to do anything special since
* timer is already configured to interrupt on the following tick
*/
_sys_clock_tick_announce();
#else
/* see if interrupt was triggered while timer was being reprogrammed */
if (stale_irq_check) {
stale_irq_check = 0;
if (_hpetMainCounterAtomic() < *_HPET_TIMER0_COMPARATOR) {
return; /* ignore "stale" interrupt */
}
}
/* configure timer to expire on next tick */
counter_last_value = *_HPET_TIMER0_COMPARATOR;
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_VAL_SET_CNF;
*_HPET_TIMER0_COMPARATOR = counter_last_value + counter_load_value;
programmed_ticks = 1;
/*
* Increment the tick because _timer_idle_exit does not account
* for the tick due to the timer interrupt itself. Also, if not in
* tickless mode, _sys_idle_elapsed_ticks will be 0.
*/
#ifdef CONFIG_MICROKERNEL
_sys_idle_elapsed_ticks++;
#else
_sys_idle_elapsed_ticks = 1;
#endif /* CONFIG_MICROKERNEL */
/*
* If we transistion from 0 elapsed ticks to 1 we need to announce the
* tick
* event to the microkernel. Other cases will have already been covered
* by
* _timer_idle_exit
*/
if (_sys_idle_elapsed_ticks == 1) {
_sys_clock_tick_announce();
}
#endif /* !CONFIG_TICKLESS_IDLE */
}
#ifdef CONFIG_TICKLESS_IDLE
/*
* Ensure that _timer_idle_enter() is never asked to idle for fewer than 2
* ticks (since this might require the timer to be reprogrammed for a deadline
* too close to the current time, resulting in a missed interrupt which would
* permanently disable the tick timer)
*/
#if (CONFIG_TICKLESS_IDLE_THRESH < 2)
#error Tickless idle threshold is too small (must be at least 2)
#endif
/**
*
* @brief Place system timer into idle state
*
* Re-program the timer to enter into the idle state for the given number of
* ticks (-1 means infinite number of ticks).
*
* @return N/A
*
* \INTERNAL IMPLEMENTATION DETAILS
* Called while interrupts are locked.
*/
void _timer_idle_enter(int32_t ticks /* system ticks */
)
{
/*
* reprogram timer to expire at the desired time (which is guaranteed
* to be at least one full tick from the current counter value)
*/
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_VAL_SET_CNF;
*_HPET_TIMER0_COMPARATOR =
(ticks >= 0) ? counter_last_value + ticks * counter_load_value
: ~(uint64_t)0;
stale_irq_check = 1;
programmed_ticks = ticks;
}
/**
*
* @brief Take system timer out of idle state
*
* Determine how long timer has been idling and reprogram it to interrupt at the
* next tick.
*
* Note that in this routine, _sys_idle_elapsed_ticks must be zero because the
* ticker has done its work and consumed all the ticks. This has to be true
* otherwise idle mode wouldn't have been entered in the first place.
*
* @return N/A
*
* \INTERNAL IMPLEMENTATION DETAILS
* Called by _IntEnt() while interrupts are locked.
*/
void _timer_idle_exit(void)
{
uint64_t currTime = _hpetMainCounterAtomic();
int32_t elapsedTicks;
uint64_t counterNextValue;
/* see if idling ended because timer expired at the desired tick */
if (currTime >= *_HPET_TIMER0_COMPARATOR) {
/*
* update # of ticks since last tick event was announced,
* so that this value is available to ISRs that run before the
* timer interrupt handler runs (which is unlikely, but could
* happen)
*/
_sys_idle_elapsed_ticks = programmed_ticks - 1;
/*
* Announce elapsed ticks to the microkernel. Note we are
* guaranteed that the timer ISR will execute first before the
* tick event is serviced.
*/
_sys_clock_tick_announce();
/* timer interrupt handler reprograms the timer for the next
* tick
*/
return;
}
/*
* idling ceased because a non-timer interrupt occurred
*
* compute how much idle time has elapsed and reprogram the timer
* to expire on the next tick; if the next tick will happen so soon
* that HPET might miss the interrupt declare that tick prematurely
* and program the timer for the tick after that
*
* note: a premature tick declaration has no significant impact on
* the microkernel, which gets informed of the correct number of elapsed
* ticks when the following tick finally occurs; however, any ISRs that
* access _sys_idle_elapsed_ticks to determine the current time may be
* misled during the (very brief) interval before the tick-in-progress
* finishes and the following tick begins
*/
elapsedTicks =
(int32_t)((currTime - counter_last_value) / counter_load_value);
counter_last_value += (uint64_t)elapsedTicks * counter_load_value;
counterNextValue = counter_last_value + counter_load_value;
if ((counterNextValue - currTime) <= HPET_COMP_DELAY) {
elapsedTicks++;
counterNextValue += counter_load_value;
counter_last_value += counter_load_value;
}
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_VAL_SET_CNF;
*_HPET_TIMER0_COMPARATOR = counterNextValue;
stale_irq_check = 1;
/*
* update # of ticks since last tick event was announced,
* so that this value is available to ISRs that run before the timer
* expires and the timer interrupt handler runs
*/
_sys_idle_elapsed_ticks = elapsedTicks;
if (_sys_idle_elapsed_ticks) {
/* Announce elapsed ticks to the microkernel */
_sys_clock_tick_announce();
}
/*
* Any elapsed ticks have been accounted for so simply set the
* programmed ticks to 1 since the timer has been programmed to fire on
* the next tick boundary.
*/
programmed_ticks = 1;
}
#endif /* CONFIG_TICKLESS_IDLE */
/**
*
* @brief Initialize and enable the system clock
*
* This routine is used to program the HPET to deliver interrupts at the
* rate specified via the 'sys_clock_us_per_tick' global variable.
*
* @return 0
*/
int _sys_clock_driver_init(struct device *device)
{
uint64_t hpetClockPeriod;
uint64_t tickFempto;
#ifndef CONFIG_TICKLESS_IDLE
uint32_t counter_load_value;
#endif
ARG_UNUSED(device);
/*
* Initial state of HPET is unknown, so put it back in a reset-like
* state (i.e. set main counter to 0 and disable interrupts)
*/
*_HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
*_HPET_MAIN_COUNTER_VALUE = 0;
/*
* Determine the comparator load value (based on a start count of 0)
* to achieve the configured tick rate.
*/
/*
* Convert the 'sys_clock_us_per_tick' value
* from microseconds to femptoseconds
*/
tickFempto = (uint64_t)sys_clock_us_per_tick * 1000000000;
/*
* This driver shall read the COUNTER_CLK_PERIOD value from the general
* capabilities register rather than rely on a board.h provide macro
* (or the global variable 'sys_clock_hw_cycles_per_tick')
* to determine the frequency of clock applied to the HPET device.
*/
/* read the clock period: units are fempto (10^-15) seconds */
hpetClockPeriod = HPET_COUNTER_CLK_PERIOD(*_HPET_GENERAL_CAPS);
/*
* compute value for the comparator register to achieve
* 'sys_clock_us_per_tick' period
*/
counter_load_value = (uint32_t)(tickFempto / hpetClockPeriod);
PRINTK("\n\nHPET: configuration: 0x%x, clock period: 0x%x (%d pico-s)\n",
(uint32_t)(*_HPET_GENERAL_CAPS),
(uint32_t)hpetClockPeriod, (uint32_t)hpetClockPeriod / 1000);
PRINTK("HPET: timer0: available interrupts mask 0x%x\n",
(uint32_t)(*_HPET_TIMER0_CONFIG_CAPS >> 32));
/* Initialize sys_clock_hw_cycles_per_tick/sec */
sys_clock_hw_cycles_per_tick = counter_load_value;
sys_clock_hw_cycles_per_sec = sys_clock_hw_cycles_per_tick *
sys_clock_ticks_per_sec;
#ifdef CONFIG_INT_LATENCY_BENCHMARK
main_count_first_irq_value = counter_load_value;
main_count_expected_value = main_count_first_irq_value;
#endif
#ifdef CONFIG_HPET_TIMER_LEGACY_EMULATION
/*
* Configure HPET replace legacy 8254 timer.
* In this case the timer0 interrupt is routed to IRQ2
* and legacy timer generates no interrupts
*/
*_HPET_GENERAL_CONFIG |= HPET_LEGACY_RT_CNF;
#endif /* CONFIG_HPET_TIMER_LEGACY_EMULATION */
#ifndef CONFIG_TICKLESS_IDLE
/*
* Set timer0 to periodic mode, ready to expire every tick
* Setting 32-bit mode during the first load of the comparator
* value is required to work around some hardware that otherwise
* does not work properly.
*/
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_TYPE_CNF | HPET_Tn_32MODE_CNF;
#else
/* set timer0 to one-shot mode, ready to expire on the first tick */
*_HPET_TIMER0_CONFIG_CAPS &= ~HPET_Tn_TYPE_CNF;
#endif /* !CONFIG_TICKLESS_IDLE */
/*
* Set the comparator register for timer0. The write to the comparator
* register is allowed due to setting the HPET_Tn_VAL_SET_CNF bit.
*/
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_VAL_SET_CNF;
*_HPET_TIMER0_COMPARATOR = counter_load_value;
/*
* After the comparator is loaded, 32-bit mode can be safely
* switched off
*/
*_HPET_TIMER0_CONFIG_CAPS &= ~HPET_Tn_32MODE_CNF;
/*
* Route interrupts to the I/O APIC. If HPET_Tn_INT_TYPE_CNF is set this
* means edge triggered interrupt mode is utilized; Otherwise level
* sensitive interrupts are used.
*/
/*
* HPET timers IRQ field is 5 bits wide, and hence, can support only
* IRQ's up to 31. Some platforms, however, use IRQs greater than 31. In
* this case program leaves the IRQ fields blank.
*/
*_HPET_TIMER0_CONFIG_CAPS =
#if CONFIG_HPET_TIMER_IRQ < 32
(*_HPET_TIMER0_CONFIG_CAPS & ~HPET_Tn_INT_ROUTE_CNF_MASK) |
(CONFIG_HPET_TIMER_IRQ << HPET_Tn_INT_ROUTE_CNF_SHIFT)
#else
(*_HPET_TIMER0_CONFIG_CAPS & ~HPET_Tn_INT_ROUTE_CNF_MASK)
#endif
#if defined(CONFIG_HPET_TIMER_LEVEL_LOW) || defined(CONFIG_HPET_TIMER_LEVEL_HIGH)
| HPET_Tn_INT_TYPE_CNF;
#else
;
#endif
/*
* Although the stub has already been "connected", the vector number
* still has to be programmed into the interrupt controller.
*/
IRQ_CONNECT(CONFIG_HPET_TIMER_IRQ, CONFIG_HPET_TIMER_IRQ_PRIORITY,
_timer_int_handler, 0, HPET_IOAPIC_FLAGS);
/* enable the IRQ in the interrupt controller */
irq_enable(CONFIG_HPET_TIMER_IRQ);
/* enable the HPET generally, and timer0 specifically */
*_HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
*_HPET_TIMER0_CONFIG_CAPS |= HPET_Tn_INT_ENB_CNF;
return 0;
}
/**
*
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*
* \INTERNAL WARNING
* If this routine is ever enhanced to return all 64 bits of the counter
* it will need to call _hpetMainCounterAtomic().
*/
uint32_t sys_cycle_get_32(void)
{
return (uint32_t) *_HPET_MAIN_COUNTER_VALUE;
}
#ifdef CONFIG_SYSTEM_CLOCK_DISABLE
/**
*
* @brief Stop announcing ticks into the kernel
*
* This routine disables the HPET so that timer interrupts are no
* longer delivered.
*
* @return N/A
*/
void sys_clock_disable(void)
{
/*
* disable the main HPET up counter and all timer interrupts;
* there is no need to lock interrupts before doing this since
* no other code alters the HPET's main configuration register
* once the driver has been initialized
*/
*_HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
}
#endif /* CONFIG_SYSTEM_CLOCK_DISABLE */
|