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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 | /* * Copyright (c) 2014 Wind River Systems, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ /** * @file * @brief Common fault handler for ARM Cortex-M * * Common fault handler for ARM Cortex-M processors. */ #include <toolchain.h> #include <sections.h> #include <nanokernel.h> #include <nano_private.h> #ifdef CONFIG_PRINTK #include <misc/printk.h> #define PR_EXC(...) printk(__VA_ARGS__) #else #define PR_EXC(...) #endif /* CONFIG_PRINTK */ #if (CONFIG_FAULT_DUMP > 0) #define FAULT_DUMP(esf, fault) _FaultDump(esf, fault) #else #define FAULT_DUMP(esf, fault) \ do { \ (void) esf; \ (void) fault; \ } while ((0)) #endif #if (CONFIG_FAULT_DUMP == 1) /** * * @brief Dump information regarding fault (FAULT_DUMP == 1) * * Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 1 * (short form). * * eg. (precise bus error escalated to hard fault): * * Fault! EXC #3, Thread: 0x200000dc, instr: 0x000011d3 * HARD FAULT: Escalation (see below)! * MMFSR: 0x00000000, BFSR: 0x00000082, UFSR: 0x00000000 * BFAR: 0xff001234 * * @return N/A */ void _FaultDump(const NANO_ESF *esf, int fault) { int escalation = 0; PR_EXC("Fault! EXC #%d, Thread: %x, instr @ %x\n", fault, sys_thread_self_get(), esf->pc); if (3 == fault) { /* hard fault */ escalation = _ScbHardFaultIsForced(); PR_EXC("HARD FAULT: %s\n", escalation ? "Escalation (see below)!" : "Bus fault on vector table read\n"); } PR_EXC("MMFSR: %x, BFSR: %x, UFSR: %x\n", __scs.scb.cfsr.byte.mmfsr.val, __scs.scb.cfsr.byte.bfsr.val, __scs.scb.cfsr.byte.ufsr.val); if (_ScbMemFaultIsMmfarValid()) { PR_EXC("MMFAR: %x\n", _ScbMemFaultAddrGet()); if (escalation) { _ScbMemFaultMmfarReset(); } } if (_ScbBusFaultIsBfarValid()) { PR_EXC("BFAR: %x\n", _ScbBusFaultAddrGet()); if (escalation) { _ScbBusFaultBfarReset(); } } /* clear USFR sticky bits */ _ScbUsageFaultAllFaultsReset(); } #endif #if (CONFIG_FAULT_DUMP == 2) /** * * @brief Dump thread information * * See _FaultDump() for example. * * @return N/A */ static void _FaultThreadShow(const NANO_ESF *esf) { PR_EXC(" Executing thread ID (thread): 0x%x\n" " Faulting instruction address: 0x%x\n", sys_thread_self_get(), esf->pc); } /** * * @brief Dump MPU fault information * * See _FaultDump() for example. * * @return N/A */ static void _MpuFault(const NANO_ESF *esf, int fromHardFault) { PR_EXC("***** MPU FAULT *****\n"); _FaultThreadShow(esf); if (_ScbMemFaultIsStacking()) { PR_EXC(" Stacking error\n"); } else if (_ScbMemFaultIsUnstacking()) { PR_EXC(" Unstacking error\n"); } else if (_ScbMemFaultIsDataAccessViolation()) { PR_EXC(" Data Access Violation\n"); if (_ScbMemFaultIsMmfarValid()) { PR_EXC(" Address: 0x%x\n", _ScbMemFaultAddrGet()); if (fromHardFault) { _ScbMemFaultMmfarReset(); } } } else if (_ScbMemFaultIsInstrAccessViolation()) { PR_EXC(" Instruction Access Violation\n"); } } /** * * @brief Dump bus fault information * * See _FaultDump() for example. * * @return N/A */ static void _BusFault(const NANO_ESF *esf, int fromHardFault) { PR_EXC("***** BUS FAULT *****\n"); _FaultThreadShow(esf); if (_ScbBusFaultIsStacking()) { PR_EXC(" Stacking error\n"); } else if (_ScbBusFaultIsUnstacking()) { PR_EXC(" Unstacking error\n"); } else if (_ScbBusFaultIsPrecise()) { PR_EXC(" Precise data bus error\n"); if (_ScbBusFaultIsBfarValid()) { PR_EXC(" Address: 0x%x\n", _ScbBusFaultAddrGet()); if (fromHardFault) { _ScbBusFaultBfarReset(); } } /* it's possible to have both a precise and imprecise fault */ if (_ScbBusFaultIsImprecise()) { PR_EXC(" Imprecise data bus error\n"); } } else if (_ScbBusFaultIsImprecise()) { PR_EXC(" Imprecise data bus error\n"); } else if (_ScbBusFaultIsInstrBusErr()) { PR_EXC(" Instruction bus error\n"); } } /** * * @brief Dump usage fault information * * See _FaultDump() for example. * * @return N/A */ static void _UsageFault(const NANO_ESF *esf) { PR_EXC("***** USAGE FAULT *****\n"); _FaultThreadShow(esf); /* bits are sticky: they stack and must be reset */ if (_ScbUsageFaultIsDivByZero()) { PR_EXC(" Division by zero\n"); } if (_ScbUsageFaultIsUnaligned()) { PR_EXC(" Unaligned memory access\n"); } if (_ScbUsageFaultIsNoCp()) { PR_EXC(" No coprocessor instructions\n"); } if (_ScbUsageFaultIsInvalidPcLoad()) { PR_EXC(" Illegal load of EXC_RETURN into PC\n"); } if (_ScbUsageFaultIsInvalidState()) { PR_EXC(" Illegal use of the EPSR\n"); } if (_ScbUsageFaultIsUndefinedInstr()) { PR_EXC(" Attempt to execute undefined instruction\n"); } _ScbUsageFaultAllFaultsReset(); } /** * * @brief Dump hard fault information * * See _FaultDump() for example. * * @return N/A */ static void _HardFault(const NANO_ESF *esf) { PR_EXC("***** HARD FAULT *****\n"); if (_ScbHardFaultIsBusErrOnVectorRead()) { PR_EXC(" Bus fault on vector table read\n"); } else if (_ScbHardFaultIsForced()) { PR_EXC(" Fault escalation (see below)\n"); if (_ScbIsMemFault()) { _MpuFault(esf, 1); } else if (_ScbIsBusFault()) { _BusFault(esf, 1); } else if (_ScbIsUsageFault()) { _UsageFault(esf); } } } /** * * @brief Dump debug monitor exception information * * See _FaultDump() for example. * * @return N/A */ static void _DebugMonitor(const NANO_ESF *esf) { PR_EXC("***** Debug monitor exception (not implemented) *****\n"); } /** * * @brief Dump reserved exception information * * See _FaultDump() for example. * * @return N/A */ static void _ReservedException(const NANO_ESF *esf, int fault) { PR_EXC("***** %s %d) *****\n", fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", fault - 16); } /** * * @brief Dump information regarding fault (FAULT_DUMP == 2) * * Dump information regarding the fault when CONFIG_FAULT_DUMP is set to 2 * (long form). * * eg. (precise bus error escalated to hard fault): * * Executing thread ID (thread): 0x200000dc * Faulting instruction address: 0x000011d3 * ***** HARD FAULT ***** * Fault escalation (see below) * ***** BUS FAULT ***** * Precise data bus error * Address: 0xff001234 * * @return N/A */ static void _FaultDump(const NANO_ESF *esf, int fault) { switch (fault) { case 3: _HardFault(esf); break; case 4: _MpuFault(esf, 0); break; case 5: _BusFault(esf, 0); break; case 6: _UsageFault(esf); break; case 12: _DebugMonitor(esf); break; default: _ReservedException(esf, fault); break; } } #endif /* FAULT_DUMP == 2 */ /** * * @brief Fault handler * * This routine is called when fatal error conditions are detected by hardware * and is responsible only for reporting the error. Once reported, it then * invokes the user provided routine _SysFatalErrorHandler() which is * responsible for implementing the error handling policy. * * Since the ESF can be either on the MSP or PSP depending if an exception or * interrupt was already being handled, it is passed a pointer to both and has * to find out on which the ESP is present. * * @param esf ESF on the stack, either MSP or PSP depending at what processor * state the exception was taken. * * @return This function does not return. */ void _Fault(const NANO_ESF *esf) { int fault = _ScbActiveVectorGet(); FAULT_DUMP(esf, fault); _SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf); } /** * * @brief Initialization of fault handling * * Turns on the desired hardware faults. * * @return N/A */ void _FaultInit(void) { _ScbDivByZeroFaultEnable(); } |