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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 | # Kconfig.dw - DesignWare SPI driver configuration options # # # Copyright (c) 2015-2016 Intel Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # menuconfig SPI_DW bool prompt "Designware SPI controller driver" depends on SPI default n help Enable support for Designware's SPI controllers. if SPI_DW config SPI_DW_ARC_AUX_REGS bool "Registers are part of ARC auxiliary registers" depends on SPI_DW && ARC default y help SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. config SPI_DW_CS_GPIO bool "SPI port CS pin is controlled via a GPIO port" depends on SPI_DW && GPIO default n config SPI_DW_INIT_PRIORITY int "Init priority" depends on SPI_DW default 70 help Device driver initialization priority. choice depends on SPI_DW && (IOAPIC || MVIC) prompt "DesignWare SPI interrupt trigger condition" default SPI_DW_RISING_EDGE config SPI_DW_FALLING_EDGE bool "Falling edge" help "DesignWare SPI uses falling edge interrupt" config SPI_DW_RISING_EDGE bool "Rising edge" help "DesignWare SPI uses rising edge interrupt" config SPI_DW_LEVEL_HIGH bool "Level high" help "DesignWare SPI uses level high interrupt" config SPI_DW_LEVEL_LOW bool "Level low" help "DesignWare SPI uses level low interrupt" endchoice choice depends on SPI_DW prompt "DesignWare SPI interrupt management logic" default SPI_DW_INTERRUPT_SINGLE_LINE config SPI_DW_INTERRUPT_SINGLE_LINE bool "Single interrupt line for all interrupts" help Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. config SPI_DW_INTERRUPT_SEPARATED_LINES bool "One line per-interrupt type (RX, TX and ERROR)" help Each interrupt gets a dedicated line endchoice config SPI_DW_CLOCK_GATE bool "Enable glock gating" depends on SPI_DW && SOC_QUARK_SE select CLOCK_CONTROL default n config SPI_DW_CLOCK_GATE_DRV_NAME string depends on SPI_DW_CLOCK_GATE default "" config SPI_DW_PORT_0 bool prompt "Designware SPI port 0" depends on SPI_DW default n help Enable Designware SPI controller port 0. config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" depends on SPI_DW_CLOCK_GATE config SPI_DW_PORT_0_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default GPIO_DW_0_NAME config SPI_DW_PORT_0_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default 0 config SPI_DW_PORT_0_DRV_NAME string prompt "Designware SPI port 0 device name" depends on SPI_DW_PORT_0 default "SPI_0" config SPI_DW_PORT_0_REGS hex prompt "Port 0 registers address" depends on SPI_DW_PORT_0 config SPI_DW_PORT_0_IRQ int "Port 0 interrupt" depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SINGLE_LINE help Interrupt number dedicated to the controller. Valid if only the controller routes all interrupt through a unique line. config SPI_DW_PORT_0_ERROR_IRQ int "Port 0 ERROR Interrupt" depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the ERROR interrupt only. RX and TX interrupt numbers need to be set as well. config SPI_DW_PORT_0_RX_IRQ int "Port 0 RX Interrupt" depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the RX interrupt only. TX and ERROR interrupt numbers need to be set as well. config SPI_DW_PORT_0_TX_IRQ int "Port 0 TX Interrupt" depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the TX interrupt only. RX and ERROR interrupt numbers need to be set as well. config SPI_DW_PORT_0_PRI int prompt "Port 0 interrupt priority" depends on SPI_DW_PORT_0 config SPI_DW_PORT_1 bool prompt "Designware SPI port 1" depends on SPI_DW default n help Enable Designware SPI controller port 1. config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" depends on SPI_DW_CLOCK_GATE config SPI_DW_PORT_1_CS_GPIO_PORT string prompt "The GPIO port which is used to control CS" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default GPIO_DW_0_NAME config SPI_DW_PORT_1_CS_GPIO_PIN int "The GPIO PIN which is used to act as a CS pin" depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO default 0 config SPI_DW_PORT_1_DRV_NAME string prompt "Designware SPI port 1 device name" depends on SPI_DW_PORT_1 default "SPI_1" config SPI_DW_PORT_1_REGS hex prompt "Port 1 registers address" depends on SPI_DW_PORT_1 config SPI_DW_PORT_1_IRQ int "Port 1 interrupt" depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SINGLE_LINE help Interrupt number dedicated to the controller. Valid if only the controller routes all interrupt through a unique line. config SPI_DW_PORT_1_ERROR_IRQ int "Port 1 ERROR Interrupt" depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the ERROR interrupt only. RX and TX interrupt numbers need to be set as well. config SPI_DW_PORT_1_RX_IRQ int "Port 1 RX Interrupt" depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the RX interrupt only. TX and ERROR interrupt numbers need to be set as well. config SPI_DW_PORT_1_TX_IRQ int "Port 1 TX Interrupt" depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES help Interrupt number dedicated to the TX interrupt only. RX and ERROR interrupt numbers need to be set as well. config SPI_DW_PORT_1_PRI int prompt "Port 1 interrupt priority" depends on SPI_DW_PORT_1 endif # SPI_DW |