Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 | /*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_lpi2c.h"
#include <stdlib.h>
#include <string.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpi2c"
#endif
/*! @brief Common sets of flags used by the driver. */
enum _lpi2c_flag_constants
{
/*! All flags which are cleared by the driver upon starting a transfer. */
kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag |
kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag |
kLPI2C_MasterDataMatchFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag |
kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag |
kLPI2C_MasterFifoErrFlag,
/*! Errors to check for. */
kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag |
kLPI2C_MasterPinLowTimeoutFlag,
/*! All flags which are cleared by the driver upon starting a transfer. */
kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveFifoErrFlag,
/*! IRQ sources enabled by the non-blocking transactional API. */
kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag |
kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag |
kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag,
/*! Errors to check for. */
kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag,
};
/* ! @brief LPI2C master fifo commands. */
enum _lpi2c_master_fifo_cmd
{
kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */
kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */
kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */
kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */
};
/*!
* @brief Default watermark values.
*
* The default watermarks are set to zero.
*/
enum _lpi2c_default_watermarks
{
kDefaultTxWatermark = 0,
kDefaultRxWatermark = 0,
};
/*! @brief States for the state machine used by transactional APIs. */
enum _lpi2c_transfer_states
{
kIdleState = 0,
kSendCommandState,
kIssueReadCommandState,
kTransferDataState,
kStopState,
kWaitForCompletionState,
};
/*! @brief Typedef for master interrupt handler. */
typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle);
/*! @brief Typedef for slave interrupt handler. */
typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle);
/*******************************************************************************
* Prototypes
******************************************************************************/
/* Not static so it can be used from fsl_lpi2c_edma.c. */
uint32_t LPI2C_GetInstance(LPI2C_Type *base);
static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
uint32_t width_ns,
uint32_t maxCycles,
uint32_t prescaler);
static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base);
static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone);
static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle);
static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags);
static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Array to map LPI2C instance number to base pointer. */
static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS;
/*! @brief Array to map LPI2C instance number to IRQ number. */
static IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Array to map LPI2C instance number to clock gate enum. */
static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS;
#if defined(LPI2C_PERIPH_CLOCKS)
/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */
static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS;
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointer to master IRQ handler for each instance. */
static lpi2c_master_isr_t s_lpi2cMasterIsr;
/*! @brief Pointers to master handles for each instance. */
static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)];
/*! @brief Pointer to slave IRQ handler for each instance. */
static lpi2c_slave_isr_t s_lpi2cSlaveIsr;
/*! @brief Pointers to slave handles for each instance. */
static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)];
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief Returns an instance number given a base address.
*
* If an invalid base address is passed, debug builds will assert. Release builds will just return
* instance number 0.
*
* @param base The LPI2C peripheral base address.
* @return LPI2C instance number starting from 0.
*/
uint32_t LPI2C_GetInstance(LPI2C_Type *base)
{
uint32_t instance;
for (instance = 0; instance < ARRAY_SIZE(kLpi2cBases); ++instance)
{
if (kLpi2cBases[instance] == base)
{
return instance;
}
}
assert(false);
return 0;
}
/*!
* @brief Computes a cycle count for a given time in nanoseconds.
* @param sourceClock_Hz LPI2C functional clock frequency in Hertz.
* @param width_ns Desired with in nanoseconds.
* @param maxCycles Maximum cycle count, determined by the number of bits wide the cycle count field is.
* @param prescaler LPI2C prescaler setting. Pass 1 if the prescaler should not be used, as for slave glitch widths.
*/
static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
uint32_t width_ns,
uint32_t maxCycles,
uint32_t prescaler)
{
assert(sourceClock_Hz > 0);
assert(prescaler > 0);
uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000);
uint32_t cycles = 0;
/* Search for the cycle count just below the desired glitch width. */
while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles))
{
++cycles;
}
/* If we end up with zero cycles, then set the filter to a single cycle unless the */
/* bus clock is greater than 10x the desired glitch width. */
if ((cycles == 0) && (busCycle_ns <= (width_ns * 10)))
{
cycles = 1;
}
return cycles;
}
/*!
* @brief Convert provided flags to status code, and clear any errors if present.
* @param base The LPI2C peripheral base address.
* @param status Current status flags value that will be checked.
* @retval #kStatus_Success
* @retval #kStatus_LPI2C_PinLowTimeout
* @retval #kStatus_LPI2C_ArbitrationLost
* @retval #kStatus_LPI2C_Nak
* @retval #kStatus_LPI2C_FifoError
*/
/* Not static so it can be used from fsl_lpi2c_edma.c. */
status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
{
status_t result = kStatus_Success;
/* Check for error. These errors cause a stop to automatically be sent. We must */
/* clear the errors before a new transfer can start. */
status &= kMasterErrorFlags;
if (status)
{
/* Select the correct error code. Ordered by severity, with bus issues first. */
if (status & kLPI2C_MasterPinLowTimeoutFlag)
{
result = kStatus_LPI2C_PinLowTimeout;
}
else if (status & kLPI2C_MasterArbitrationLostFlag)
{
result = kStatus_LPI2C_ArbitrationLost;
}
else if (status & kLPI2C_MasterNackDetectFlag)
{
result = kStatus_LPI2C_Nak;
}
else if (status & kLPI2C_MasterFifoErrFlag)
{
result = kStatus_LPI2C_FifoError;
}
else
{
assert(false);
}
/* Clear the flags. */
LPI2C_MasterClearStatusFlags(base, status);
/* Reset fifos. These flags clear automatically. */
base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
}
return result;
}
/*!
* @brief Wait until there is room in the tx fifo.
* @param base The LPI2C peripheral base address.
* @retval #kStatus_Success
* @retval #kStatus_LPI2C_PinLowTimeout
* @retval #kStatus_LPI2C_ArbitrationLost
* @retval #kStatus_LPI2C_Nak
* @retval #kStatus_LPI2C_FifoError
*/
static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
{
uint32_t status;
size_t txCount;
size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base);
#if LPI2C_WAIT_TIMEOUT
uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
#endif
do
{
status_t result;
/* Get the number of words in the tx fifo and compute empty slots. */
LPI2C_MasterGetFifoCounts(base, NULL, &txCount);
txCount = txFifoSize - txCount;
/* Check for error flags. */
status = LPI2C_MasterGetStatusFlags(base);
result = LPI2C_MasterCheckAndClearError(base, status);
if (result)
{
return result;
}
#if LPI2C_WAIT_TIMEOUT
} while ((!txCount) && (--waitTimes));
if (waitTimes == 0)
{
return kStatus_LPI2C_Timeout;
}
#else
} while (!txCount);
#endif
return kStatus_Success;
}
/*!
* @brief Make sure the bus isn't already busy.
*
* A busy bus is allowed if we are the one driving it.
*
* @param base The LPI2C peripheral base address.
* @retval #kStatus_Success
* @retval #kStatus_LPI2C_Busy
*/
/* Not static so it can be used from fsl_lpi2c_edma.c. */
status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
{
uint32_t status = LPI2C_MasterGetStatusFlags(base);
if ((status & kLPI2C_MasterBusBusyFlag) && (!(status & kLPI2C_MasterBusyFlag)))
{
return kStatus_LPI2C_Busy;
}
return kStatus_Success;
}
/*!
* brief Provides a default configuration for the LPI2C master peripheral.
*
* This function provides the following default configuration for the LPI2C master peripheral:
* code
* masterConfig->enableMaster = true;
* masterConfig->debugEnable = false;
* masterConfig->ignoreAck = false;
* masterConfig->pinConfig = kLPI2C_2PinOpenDrain;
* masterConfig->baudRate_Hz = 100000U;
* masterConfig->busIdleTimeout_ns = 0;
* masterConfig->pinLowTimeout_ns = 0;
* masterConfig->sdaGlitchFilterWidth_ns = 0;
* masterConfig->sclGlitchFilterWidth_ns = 0;
* masterConfig->hostRequest.enable = false;
* masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin;
* masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh;
* endcode
*
* After calling this function, you can override any settings in order to customize the configuration,
* prior to initializing the master driver with LPI2C_MasterInit().
*
* param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t.
*/
void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig)
{
/* Initializes the configure structure to zero. */
memset(masterConfig, 0, sizeof(*masterConfig));
masterConfig->enableMaster = true;
masterConfig->debugEnable = false;
masterConfig->enableDoze = true;
masterConfig->ignoreAck = false;
masterConfig->pinConfig = kLPI2C_2PinOpenDrain;
masterConfig->baudRate_Hz = 100000U;
masterConfig->busIdleTimeout_ns = 0;
masterConfig->pinLowTimeout_ns = 0;
masterConfig->sdaGlitchFilterWidth_ns = 0;
masterConfig->sclGlitchFilterWidth_ns = 0;
masterConfig->hostRequest.enable = false;
masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin;
masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh;
}
/*!
* brief Initializes the LPI2C master peripheral.
*
* This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user
* provided configuration. A software reset is performed prior to configuration.
*
* param base The LPI2C peripheral base address.
* param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of
* defaults
* that you can override.
* param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors,
* filter widths, and timeout periods.
*/
void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
{
uint32_t prescaler;
uint32_t cycles;
uint32_t cfgr2;
uint32_t value;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = LPI2C_GetInstance(base);
/* Ungate the clock. */
CLOCK_EnableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Ungate the functional clock in initialize function. */
CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset peripheral before configuring it. */
LPI2C_MasterReset(base);
/* Doze bit: 0 is enable, 1 is disable */
base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze));
/* host request */
value = base->MCFGR0;
value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK));
value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) |
LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) |
LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source);
base->MCFGR0 = value;
/* pin config and ignore ack */
value = base->MCFGR1;
value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK);
value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig);
value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck);
base->MCFGR1 = value;
LPI2C_MasterSetWatermarks(base, kDefaultTxWatermark, kDefaultRxWatermark);
LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz);
/* Configure glitch filters and bus idle and pin low timeouts. */
prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT;
cfgr2 = base->MCFGR2;
if (masterConfig->busIdleTimeout_ns)
{
cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns,
(LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK;
cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles);
}
if (masterConfig->sdaGlitchFilterWidth_ns)
{
cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns,
(LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 1);
cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK;
cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles);
}
if (masterConfig->sclGlitchFilterWidth_ns)
{
cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns,
(LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 1);
cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK;
cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles);
}
base->MCFGR2 = cfgr2;
if (masterConfig->pinLowTimeout_ns)
{
cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256,
(LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles);
}
LPI2C_MasterEnable(base, masterConfig->enableMaster);
}
/*!
* brief Deinitializes the LPI2C master peripheral.
*
* This function disables the LPI2C master peripheral and gates the clock. It also performs a software
* reset to restore the peripheral to reset conditions.
*
* param base The LPI2C peripheral base address.
*/
void LPI2C_MasterDeinit(LPI2C_Type *base)
{
/* Restore to reset state. */
LPI2C_MasterReset(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = LPI2C_GetInstance(base);
/* Gate clock. */
CLOCK_DisableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Gate the functional clock. */
CLOCK_DisableClock(kLpi2cPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* brief Configures LPI2C master data match feature.
*
* param base The LPI2C peripheral base address.
* param config Settings for the data match feature.
*/
void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config)
{
/* Disable master mode. */
bool wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
LPI2C_MasterEnable(base, false);
base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode);
base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly);
base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1);
/* Restore master mode. */
if (wasEnabled)
{
LPI2C_MasterEnable(base, true);
}
}
/*!
* brief Sets the I2C bus frequency for master transactions.
*
* The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud
* rate. Do not call this function during a transfer, or the transfer is aborted.
*
* note Please note that the second parameter is the clock frequency of LPI2C module, the third
* parameter means user configured bus baudrate, this implementation is different from other I2C drivers
* which use baudrate configuration as second parameter and source clock frequency as third parameter.
*
* param base The LPI2C peripheral base address.
* param sourceClock_Hz LPI2C functional clock frequency in Hertz.
* param baudRate_Hz Requested bus frequency in Hertz.
*/
void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz)
{
uint32_t prescale = 0;
uint32_t bestPre = 0;
uint32_t bestClkHi = 0;
uint32_t absError = 0;
uint32_t bestError = 0xffffffffu;
uint32_t value;
uint32_t clkHiCycle;
uint32_t computedRate;
int i;
bool wasEnabled;
/* Disable master mode. */
wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
LPI2C_MasterEnable(base, false);
/* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */
/* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */
for (prescale = 1; (prescale <= 128) && (bestError != 0); prescale = 2 * prescale)
{
for (clkHiCycle = 1; clkHiCycle < 32; clkHiCycle++)
{
if (clkHiCycle == 1)
{
computedRate = (sourceClock_Hz / prescale) / (1 + 3 + 2 + 2 / prescale);
}
else
{
computedRate = (sourceClock_Hz / prescale) / (3 * clkHiCycle + 2 + 2 / prescale);
}
absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz;
if (absError < bestError)
{
bestPre = prescale;
bestClkHi = clkHiCycle;
bestError = absError;
/* If the error is 0, then we can stop searching because we won't find a better match. */
if (absError == 0)
{
break;
}
}
}
}
/* Standard, fast, fast mode plus and ultra-fast transfers. */
value = LPI2C_MCCR0_CLKHI(bestClkHi);
if (bestClkHi < 2)
{
value |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1);
}
else
{
value |= LPI2C_MCCR0_CLKLO(2 * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2);
}
base->MCCR0 = value;
for (i = 0; i < 8; i++)
{
if (bestPre == (1U << i))
{
bestPre = i;
break;
}
}
base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre);
/* Restore master mode. */
if (wasEnabled)
{
LPI2C_MasterEnable(base, true);
}
}
/*!
* brief Sends a START signal and slave address on the I2C bus.
*
* This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
* that another master is not occupying the bus. Then a START signal is transmitted, followed by the
* 7-bit address specified in the a address parameter. Note that this function does not actually wait
* until the START and address are successfully sent on the bus before returning.
*
* param base The LPI2C peripheral base address.
* param address 7-bit slave device address, in bits [6:0].
* param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set
* the R/w bit (bit 0) in the transmitted slave address.
* retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
* retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
*/
status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir)
{
/* Return an error if the bus is already in use not by us. */
status_t result = LPI2C_CheckForBusyBus(base);
if (result)
{
return result;
}
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, kMasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
/* Wait until there is room in the fifo. */
result = LPI2C_MasterWaitForTxReady(base);
if (result)
{
return result;
}
/* Issue start command. */
base->MTDR = kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir);
return kStatus_Success;
}
/*!
* brief Sends a STOP signal on the I2C bus.
*
* This function does not return until the STOP signal is seen on the bus, or an error occurs.
*
* param base The LPI2C peripheral base address.
* retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated.
* retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
* retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
* retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
* retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
* retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
*/
status_t LPI2C_MasterStop(LPI2C_Type *base)
{
/* Wait until there is room in the fifo. */
status_t result = LPI2C_MasterWaitForTxReady(base);
if (result)
{
return result;
}
/* Send the STOP signal */
base->MTDR = kStopCmd;
/* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */
/* Also check for errors while waiting. */
#if LPI2C_WAIT_TIMEOUT
uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
#endif
#if LPI2C_WAIT_TIMEOUT
while ((result == kStatus_Success) && (--waitTimes))
#else
while (result == kStatus_Success)
#endif
{
uint32_t status = LPI2C_MasterGetStatusFlags(base);
/* Check for error flags. */
result = LPI2C_MasterCheckAndClearError(base, status);
/* Check if the stop was sent successfully. */
if (status & kLPI2C_MasterStopDetectFlag)
{
LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag);
break;
}
}
#if LPI2C_WAIT_TIMEOUT
if (waitTimes == 0)
{
return kStatus_LPI2C_Timeout;
}
#endif
return result;
}
/*!
* brief Performs a polling receive transfer on the I2C bus.
*
* param base The LPI2C peripheral base address.
* param rxBuff The pointer to the data to be transferred.
* param rxSize The length in bytes of the data to be transferred.
* retval #kStatus_Success Data was received successfully.
* retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
* retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
* retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
* retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
* retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
*/
status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
{
status_t result;
uint8_t *buf;
assert(rxBuff);
/* Handle empty read. */
if (!rxSize)
{
return kStatus_Success;
}
/* Wait until there is room in the command fifo. */
result = LPI2C_MasterWaitForTxReady(base);
if (result)
{
return result;
}
/* Issue command to receive data. */
base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(rxSize - 1);
#if LPI2C_WAIT_TIMEOUT
uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
#endif
/* Receive data */
buf = (uint8_t *)rxBuff;
while (rxSize--)
{
/* Read LPI2C receive fifo register. The register includes a flag to indicate whether */
/* the FIFO is empty, so we can both get the data and check if we need to keep reading */
/* using a single register read. */
uint32_t value;
do
{
/* Check for errors. */
result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base));
if (result)
{
return result;
}
value = base->MRDR;
#if LPI2C_WAIT_TIMEOUT
} while ((value & LPI2C_MRDR_RXEMPTY_MASK) && (--waitTimes));
if (waitTimes == 0)
{
return kStatus_LPI2C_Timeout;
}
#else
} while (value & LPI2C_MRDR_RXEMPTY_MASK);
#endif
*buf++ = value & LPI2C_MRDR_DATA_MASK;
}
return kStatus_Success;
}
/*!
* brief Performs a polling send transfer on the I2C bus.
*
* Sends up to a txSize number of bytes to the previously addressed slave device. The slave may
* reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
* function returns #kStatus_LPI2C_Nak.
*
* param base The LPI2C peripheral base address.
* param txBuff The pointer to the data to be transferred.
* param txSize The length in bytes of the data to be transferred.
* retval #kStatus_Success Data was sent successfully.
* retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
* retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
* retval #kStatus_LPI2C_FifoError FIFO under run or over run.
* retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
* retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
*/
status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize)
{
uint8_t *buf = (uint8_t *)txBuff;
assert(txBuff);
/* Send data buffer */
while (txSize--)
{
/* Wait until there is room in the fifo. This also checks for errors. */
status_t result = LPI2C_MasterWaitForTxReady(base);
if (result)
{
return result;
}
/* Write byte into LPI2C master data register. */
base->MTDR = *buf++;
}
return kStatus_Success;
}
/*!
* brief Performs a master polling transfer on the I2C bus.
*
* note The API does not return until the transfer succeeds or fails due
* to error happens during transfer.
*
* param base The LPI2C peripheral base address.
* param transfer Pointer to the transfer structure.
* retval #kStatus_Success Data was received successfully.
* retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus.
* retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte.
* retval #kStatus_LPI2C_FifoError FIFO under run or overrun.
* retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error.
* retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout.
*/
status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer)
{
status_t result = kStatus_Success;
uint16_t commandBuffer[7];
uint32_t cmdCount = 0;
assert(transfer);
assert(transfer->subaddressSize <= sizeof(transfer->subaddress));
/* Return an error if the bus is already in use not by us. */
result = LPI2C_CheckForBusyBus(base);
if (result)
{
return result;
}
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, kMasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
lpi2c_direction_t direction = transfer->subaddressSize ? kLPI2C_Write : transfer->direction;
if (!(transfer->flags & kLPI2C_TransferNoStartFlag))
{
commandBuffer[cmdCount++] =
(uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction);
}
/* Subaddress, MSB first. */
if (transfer->subaddressSize)
{
uint32_t subaddressRemaining = transfer->subaddressSize;
while (subaddressRemaining--)
{
uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
commandBuffer[cmdCount++] = subaddressByte;
}
}
/* Reads need special handling. */
if ((transfer->dataSize) && (transfer->direction == kLPI2C_Read))
{
/* Need to send repeated start if switching directions to read. */
if (direction == kLPI2C_Write)
{
commandBuffer[cmdCount++] =
(uint16_t)kStartCmd |
(uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read);
}
}
/* Send command buffer */
uint32_t index = 0;
while (cmdCount--)
{
/* Wait until there is room in the fifo. This also checks for errors. */
result = LPI2C_MasterWaitForTxReady(base);
if (result)
{
return result;
}
/* Write byte into LPI2C master data register. */
base->MTDR = commandBuffer[index];
index++;
}
/* Transmit data. */
if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0))
{
/* Send Data. */
result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize);
}
/* Receive Data. */
if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0))
{
result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize);
}
if (result)
{
return result;
}
if ((transfer->flags & kLPI2C_TransferNoStopFlag) == 0)
{
result = LPI2C_MasterStop(base);
}
return result;
}
/*!
* brief Creates a new handle for the LPI2C master non-blocking APIs.
*
* The creation of a handle is for use with the non-blocking APIs. Once a handle
* is created, there is not a corresponding destroy handle. If the user wants to
* terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.
*
*
* note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
* that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
* enable the associated INTMUX IRQ in application.
*
* param base The LPI2C peripheral base address.
* param[out] handle Pointer to the LPI2C master driver handle.
* param callback User provided pointer to the asynchronous callback function.
* param userData User provided pointer to the application callback data.
*/
void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
lpi2c_master_handle_t *handle,
lpi2c_master_transfer_callback_t callback,
void *userData)
{
uint32_t instance;
assert(handle);
/* Clear out the handle. */
memset(handle, 0, sizeof(*handle));
/* Look up instance number */
instance = LPI2C_GetInstance(base);
/* Save base and instance. */
handle->completionCallback = callback;
handle->userData = userData;
/* Save this handle for IRQ use. */
s_lpi2cMasterHandle[instance] = handle;
/* Set irq handler. */
s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ;
/* Clear internal IRQ enables and enable NVIC IRQ. */
LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags);
/* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.
In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable
INTMUX IRQ in application code. */
EnableIRQ(kLpi2cIrqs[instance]);
}
/*!
* @brief Execute states until FIFOs are exhausted.
* @param handle Master nonblocking driver handle.
* @param[out] isDone Set to true if the transfer has completed.
* @retval #kStatus_Success
* @retval #kStatus_LPI2C_PinLowTimeout
* @retval #kStatus_LPI2C_ArbitrationLost
* @retval #kStatus_LPI2C_Nak
* @retval #kStatus_LPI2C_FifoError
*/
static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone)
{
uint32_t status;
status_t result = kStatus_Success;
lpi2c_master_transfer_t *xfer;
size_t txCount;
size_t rxCount;
size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base);
bool state_complete = false;
/* Set default isDone return value. */
*isDone = false;
/* Check for errors. */
status = LPI2C_MasterGetStatusFlags(base);
result = LPI2C_MasterCheckAndClearError(base, status);
if (result)
{
return result;
}
/* Get pointer to private data. */
xfer = &handle->transfer;
/* Get fifo counts and compute room in tx fifo. */
LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount);
txCount = txFifoSize - txCount;
while (!state_complete)
{
/* Execute the state. */
switch (handle->state)
{
case kSendCommandState:
{
/* Make sure there is room in the tx fifo for the next command. */
if (!txCount--)
{
state_complete = true;
break;
}
/* Issue command. buf is a uint8_t* pointing at the uint16 command array. */
base->MTDR = *(uint16_t *)handle->buf;
handle->buf += sizeof(uint16_t);
/* Count down until all commands are sent. */
if (--handle->remainingBytes == 0)
{
/* Choose next state and set up buffer pointer and count. */
if (xfer->dataSize)
{
/* Either a send or receive transfer is next. */
handle->state = kTransferDataState;
handle->buf = (uint8_t *)xfer->data;
handle->remainingBytes = xfer->dataSize;
if (xfer->direction == kLPI2C_Read)
{
/* Disable TX interrupt */
LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag);
}
}
else
{
/* No transfer, so move to stop state. */
handle->state = kStopState;
}
}
break;
}
case kIssueReadCommandState:
/* Make sure there is room in the tx fifo for the read command. */
if (!txCount--)
{
state_complete = true;
break;
}
base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1);
/* Move to transfer state. */
handle->state = kTransferDataState;
if (xfer->direction == kLPI2C_Read)
{
/* Disable TX interrupt */
LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag);
}
break;
case kTransferDataState:
if (xfer->direction == kLPI2C_Write)
{
/* Make sure there is room in the tx fifo. */
if (!txCount--)
{
state_complete = true;
break;
}
/* Put byte to send in fifo. */
base->MTDR = *(handle->buf)++;
}
else
{
/* XXX handle receive sizes > 256, use kIssueReadCommandState */
/* Make sure there is data in the rx fifo. */
if (!rxCount--)
{
state_complete = true;
break;
}
/* Read byte from fifo. */
*(handle->buf)++ = base->MRDR & LPI2C_MRDR_DATA_MASK;
}
/* Move to stop when the transfer is done. */
if (--handle->remainingBytes == 0)
{
handle->state = kStopState;
}
break;
case kStopState:
/* Only issue a stop transition if the caller requested it. */
if ((xfer->flags & kLPI2C_TransferNoStopFlag) == 0)
{
/* Make sure there is room in the tx fifo for the stop command. */
if (!txCount--)
{
state_complete = true;
break;
}
base->MTDR = kStopCmd;
}
else
{
/* Caller doesn't want to send a stop, so we're done now. */
*isDone = true;
state_complete = true;
break;
}
handle->state = kWaitForCompletionState;
break;
case kWaitForCompletionState:
/* We stay in this state until the stop state is detected. */
if (status & kLPI2C_MasterStopDetectFlag)
{
*isDone = true;
}
state_complete = true;
break;
default:
assert(false);
break;
}
}
return result;
}
/*!
* @brief Prepares the transfer state machine and fills in the command buffer.
* @param handle Master nonblocking driver handle.
*/
static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle)
{
lpi2c_master_transfer_t *xfer = &handle->transfer;
/* Handle no start option. */
if (xfer->flags & kLPI2C_TransferNoStartFlag)
{
if (xfer->direction == kLPI2C_Read)
{
/* Need to issue read command first. */
handle->state = kIssueReadCommandState;
}
else
{
/* Start immediately in the data transfer state. */
handle->state = kTransferDataState;
}
handle->buf = (uint8_t *)xfer->data;
handle->remainingBytes = xfer->dataSize;
}
else
{
uint16_t *cmd = (uint16_t *)&handle->commandBuffer;
uint32_t cmdCount = 0;
/* Initial direction depends on whether a subaddress was provided, and of course the actual */
/* data transfer direction. */
lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction;
/* Start command. */
cmd[cmdCount++] =
(uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction);
/* Subaddress, MSB first. */
if (xfer->subaddressSize)
{
uint32_t subaddressRemaining = xfer->subaddressSize;
while (subaddressRemaining--)
{
uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff;
cmd[cmdCount++] = subaddressByte;
}
}
/* Reads need special handling. */
if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read))
{
/* Need to send repeated start if switching directions to read. */
if (direction == kLPI2C_Write)
{
cmd[cmdCount++] = (uint16_t)kStartCmd |
(uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read);
}
/* Read command. */
cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1);
}
/* Set up state machine for transferring the commands. */
handle->state = kSendCommandState;
handle->remainingBytes = cmdCount;
handle->buf = (uint8_t *)&handle->commandBuffer;
}
}
/*!
* brief Performs a non-blocking transaction on the I2C bus.
*
* param base The LPI2C peripheral base address.
* param handle Pointer to the LPI2C master driver handle.
* param transfer The pointer to the transfer descriptor.
* retval #kStatus_Success The transaction was started successfully.
* retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking
* transaction is already in progress.
*/
status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base,
lpi2c_master_handle_t *handle,
lpi2c_master_transfer_t *transfer)
{
status_t result;
assert(handle);
assert(transfer);
assert(transfer->subaddressSize <= sizeof(transfer->subaddress));
/* Return busy if another transaction is in progress. */
if (handle->state != kIdleState)
{
return kStatus_LPI2C_Busy;
}
/* Return an error if the bus is already in use not by us. */
result = LPI2C_CheckForBusyBus(base);
if (result)
{
return result;
}
/* Disable LPI2C IRQ sources while we configure stuff. */
LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags);
/* Save transfer into handle. */
handle->transfer = *transfer;
/* Generate commands to send. */
LPI2C_InitTransferStateMachine(handle);
/* Clear all flags. */
LPI2C_MasterClearStatusFlags(base, kMasterClearFlags);
/* Turn off auto-stop option. */
base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK;
/* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
LPI2C_MasterEnableInterrupts(base, kMasterIrqFlags);
return result;
}
/*!
* brief Returns number of bytes transferred so far.
* param base The LPI2C peripheral base address.
* param handle Pointer to the LPI2C master driver handle.
* param[out] count Number of bytes transferred so far by the non-blocking transaction.
* retval #kStatus_Success
* retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
*/
status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count)
{
assert(handle);
if (!count)
{
return kStatus_InvalidArgument;
}
/* Catch when there is not an active transfer. */
if (handle->state == kIdleState)
{
*count = 0;
return kStatus_NoTransferInProgress;
}
uint8_t state;
uint16_t remainingBytes;
uint32_t dataSize;
/* Cache some fields with IRQs disabled. This ensures all field values */
/* are synchronized with each other during an ongoing transfer. */
uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base);
LPI2C_MasterDisableInterrupts(base, irqs);
state = handle->state;
remainingBytes = handle->remainingBytes;
dataSize = handle->transfer.dataSize;
LPI2C_MasterEnableInterrupts(base, irqs);
/* Get transfer count based on current transfer state. */
switch (state)
{
case kIdleState:
case kSendCommandState:
case kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */
*count = 0;
break;
case kTransferDataState:
*count = dataSize - remainingBytes;
break;
case kStopState:
case kWaitForCompletionState:
default:
*count = dataSize;
break;
}
return kStatus_Success;
}
/*!
* brief Terminates a non-blocking LPI2C master transmission early.
*
* note It is not safe to call this function from an IRQ handler that has a higher priority than the
* LPI2C peripheral's IRQ priority.
*
* param base The LPI2C peripheral base address.
* param handle Pointer to the LPI2C master driver handle.
* retval #kStatus_Success A transaction was successfully aborted.
* retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress.
*/
void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
{
if (handle->state != kIdleState)
{
/* Disable internal IRQ enables. */
LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags);
/* Reset fifos. */
base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
/* Send a stop command to finalize the transfer. */
base->MTDR = kStopCmd;
/* Reset handle. */
handle->state = kIdleState;
}
}
/*!
* brief Reusable routine to handle master interrupts.
* note This function does not need to be called unless you are reimplementing the
* nonblocking API's interrupt handler routines to add special functionality.
* param base The LPI2C peripheral base address.
* param handle Pointer to the LPI2C master driver handle.
*/
void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle)
{
bool isDone;
status_t result;
/* Don't do anything if we don't have a valid handle. */
if (!handle)
{
return;
}
if (handle->state == kIdleState)
{
return;
}
result = LPI2C_RunTransferStateMachine(base, handle, &isDone);
if (isDone || (result != kStatus_Success))
{
/* XXX need to handle data that may be in rx fifo below watermark level? */
/* XXX handle error, terminate xfer */
/* Disable internal IRQ enables. */
LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags);
/* Set handle to idle state. */
handle->state = kIdleState;
/* Invoke callback. */
if (handle->completionCallback)
{
handle->completionCallback(base, handle, result, handle->userData);
}
}
}
/*!
* brief Provides a default configuration for the LPI2C slave peripheral.
*
* This function provides the following default configuration for the LPI2C slave peripheral:
* code
* slaveConfig->enableSlave = true;
* slaveConfig->address0 = 0U;
* slaveConfig->address1 = 0U;
* slaveConfig->addressMatchMode = kLPI2C_MatchAddress0;
* slaveConfig->filterDozeEnable = true;
* slaveConfig->filterEnable = true;
* slaveConfig->enableGeneralCall = false;
* slaveConfig->sclStall.enableAck = false;
* slaveConfig->sclStall.enableTx = true;
* slaveConfig->sclStall.enableRx = true;
* slaveConfig->sclStall.enableAddress = true;
* slaveConfig->ignoreAck = false;
* slaveConfig->enableReceivedAddressRead = false;
* slaveConfig->sdaGlitchFilterWidth_ns = 0;
* slaveConfig->sclGlitchFilterWidth_ns = 0;
* slaveConfig->dataValidDelay_ns = 0;
* slaveConfig->clockHoldTime_ns = 0;
* endcode
*
* After calling this function, override any settings to customize the configuration,
* prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a
* address0 member of the configuration structure with the desired slave address.
*
* param[out] slaveConfig User provided configuration structure that is set to default values. Refer to
* #lpi2c_slave_config_t.
*/
void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig)
{
/* Initializes the configure structure to zero. */
memset(slaveConfig, 0, sizeof(*slaveConfig));
slaveConfig->enableSlave = true;
slaveConfig->address0 = 0U;
slaveConfig->address1 = 0U;
slaveConfig->addressMatchMode = kLPI2C_MatchAddress0;
slaveConfig->filterDozeEnable = true;
slaveConfig->filterEnable = true;
slaveConfig->enableGeneralCall = false;
slaveConfig->sclStall.enableAck = false;
slaveConfig->sclStall.enableTx = true;
slaveConfig->sclStall.enableRx = true;
slaveConfig->sclStall.enableAddress = false;
slaveConfig->ignoreAck = false;
slaveConfig->enableReceivedAddressRead = false;
slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */
slaveConfig->sclGlitchFilterWidth_ns = 0;
slaveConfig->dataValidDelay_ns = 0;
slaveConfig->clockHoldTime_ns = 0;
}
/*!
* brief Initializes the LPI2C slave peripheral.
*
* This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user
* provided configuration.
*
* param base The LPI2C peripheral base address.
* param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults
* that you can override.
* param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths,
* data valid delay, and clock hold time.
*/
void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = LPI2C_GetInstance(base);
/* Ungate the clock. */
CLOCK_EnableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Ungate the functional clock in initialize function. */
CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Restore to reset conditions. */
LPI2C_SlaveReset(base);
/* Configure peripheral. */
base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1);
base->SCFGR1 =
LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) |
LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) |
LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) |
LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) |
LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress);
base->SCFGR2 =
LPI2C_SCFGR2_FILTSDA(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns,
(LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT), 1)) |
LPI2C_SCFGR2_FILTSCL(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns,
(LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT), 1)) |
LPI2C_SCFGR2_DATAVD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns,
(LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 1)) |
LPI2C_SCFGR2_CLKHOLD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns,
(LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT), 1));
/* Save SCR to last so we don't enable slave until it is configured */
base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) |
LPI2C_SCR_SEN(slaveConfig->enableSlave);
}
/*!
* brief Deinitializes the LPI2C slave peripheral.
*
* This function disables the LPI2C slave peripheral and gates the clock. It also performs a software
* reset to restore the peripheral to reset conditions.
*
* param base The LPI2C peripheral base address.
*/
void LPI2C_SlaveDeinit(LPI2C_Type *base)
{
LPI2C_SlaveReset(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
uint32_t instance = LPI2C_GetInstance(base);
/* Gate the clock. */
CLOCK_DisableClock(kLpi2cClocks[instance]);
#if defined(LPI2C_PERIPH_CLOCKS)
/* Gate the functional clock. */
CLOCK_DisableClock(kLpi2cPeriphClocks[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Convert provided flags to status code, and clear any errors if present.
* @param base The LPI2C peripheral base address.
* @param status Current status flags value that will be checked.
* @retval #kStatus_Success
* @retval #kStatus_LPI2C_BitError
* @retval #kStatus_LPI2C_FifoError
*/
static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags)
{
status_t result = kStatus_Success;
flags &= kSlaveErrorFlags;
if (flags)
{
if (flags & kLPI2C_SlaveBitErrFlag)
{
result = kStatus_LPI2C_BitError;
}
else if (flags & kLPI2C_SlaveFifoErrFlag)
{
result = kStatus_LPI2C_FifoError;
}
else
{
assert(false);
}
/* Clear the errors. */
LPI2C_SlaveClearStatusFlags(base, flags);
}
return result;
}
/*!
* brief Performs a polling send transfer on the I2C bus.
*
* param base The LPI2C peripheral base address.
* param txBuff The pointer to the data to be transferred.
* param txSize The length in bytes of the data to be transferred.
* param[out] actualTxSize
* return Error or success status returned by API.
*/
status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize)
{
uint8_t *buf = (uint8_t *)txBuff;
size_t remaining = txSize;
assert(txBuff);
#if LPI2C_WAIT_TIMEOUT
uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
#endif
while (remaining)
{
uint32_t flags;
status_t result;
/* Wait until we can transmit. */
do
{
/* Check for errors */
flags = LPI2C_SlaveGetStatusFlags(base);
result = LPI2C_SlaveCheckAndClearError(base, flags);
if (result)
{
if (actualTxSize)
{
*actualTxSize = txSize - remaining;
}
return result;
}
#if LPI2C_WAIT_TIMEOUT
} while (
(!(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) &&
(--waitTimes));
if (waitTimes == 0)
{
return kStatus_LPI2C_Timeout;
}
#else
} while (
!(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)));
#endif
/* Send a byte. */
if (flags & kLPI2C_SlaveTxReadyFlag)
{
base->STDR = *buf++;
--remaining;
}
/* Exit loop if we see a stop or restart */
if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))
{
LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
break;
}
}
if (actualTxSize)
{
*actualTxSize = txSize - remaining;
}
return kStatus_Success;
}
/*!
* brief Performs a polling receive transfer on the I2C bus.
*
* param base The LPI2C peripheral base address.
* param rxBuff The pointer to the data to be transferred.
* param rxSize The length in bytes of the data to be transferred.
* param[out] actualRxSize
* return Error or success status returned by API.
*/
status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize)
{
uint8_t *buf = (uint8_t *)rxBuff;
size_t remaining = rxSize;
assert(rxBuff);
#if LPI2C_WAIT_TIMEOUT
uint32_t waitTimes = LPI2C_WAIT_TIMEOUT;
#endif
while (remaining)
{
uint32_t flags;
status_t result;
/* Wait until we can receive. */
do
{
/* Check for errors */
flags = LPI2C_SlaveGetStatusFlags(base);
result = LPI2C_SlaveCheckAndClearError(base, flags);
if (result)
{
if (actualRxSize)
{
*actualRxSize = rxSize - remaining;
}
return result;
}
#if LPI2C_WAIT_TIMEOUT
} while (
(!(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) &&
(--waitTimes));
if (waitTimes == 0)
{
return kStatus_LPI2C_Timeout;
}
#else
} while (
!(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)));
#endif
/* Receive a byte. */
if (flags & kLPI2C_SlaveRxReadyFlag)
{
*buf++ = base->SRDR & LPI2C_SRDR_DATA_MASK;
--remaining;
}
/* Exit loop if we see a stop or restart */
if (flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))
{
LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag);
break;
}
}
if (actualRxSize)
{
*actualRxSize = rxSize - remaining;
}
return kStatus_Success;
}
/*!
* brief Creates a new handle for the LPI2C slave non-blocking APIs.
*
* The creation of a handle is for use with the non-blocking APIs. Once a handle
* is created, there is not a corresponding destroy handle. If the user wants to
* terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.
*
* note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
* that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
* enable the associated INTMUX IRQ in application.
* param base The LPI2C peripheral base address.
* param[out] handle Pointer to the LPI2C slave driver handle.
* param callback User provided pointer to the asynchronous callback function.
* param userData User provided pointer to the application callback data.
*/
void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
lpi2c_slave_handle_t *handle,
lpi2c_slave_transfer_callback_t callback,
void *userData)
{
uint32_t instance;
assert(handle);
/* Clear out the handle. */
memset(handle, 0, sizeof(*handle));
/* Look up instance number */
instance = LPI2C_GetInstance(base);
/* Save base and instance. */
handle->callback = callback;
handle->userData = userData;
/* Save this handle for IRQ use. */
s_lpi2cSlaveHandle[instance] = handle;
/* Set irq handler. */
s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ;
/* Clear internal IRQ enables and enable NVIC IRQ. */
LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags);
EnableIRQ(kLpi2cIrqs[instance]);
/* Nack by default. */
base->STAR = LPI2C_STAR_TXNACK_MASK;
}
/*!
* brief Starts accepting slave transfers.
*
* Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing
* transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
* callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked
* from the interrupt context.
*
* The set of events received by the callback is customizable. To do so, set the a eventMask parameter to
* the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive.
* The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
* to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
* receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as
* a convenient way to enable all events.
*
* param base The LPI2C peripheral base address.
* param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
* param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify
* which events to send to the callback. Other accepted values are 0 to get a default set of
* only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events.
*
* retval #kStatus_Success Slave transfers were successfully started.
* retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle.
*/
status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask)
{
uint32_t status;
assert(handle);
/* Return busy if another transaction is in progress. */
if (handle->isBusy)
{
return kStatus_LPI2C_Busy;
}
/* Return an error if the bus is already in use not by us. */
status = LPI2C_SlaveGetStatusFlags(base);
if ((status & kLPI2C_SlaveBusBusyFlag) && (!(status & kLPI2C_SlaveBusyFlag)))
{
return kStatus_LPI2C_Busy;
}
/* Disable LPI2C IRQ sources while we configure stuff. */
LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags);
/* Clear transfer in handle. */
memset(&handle->transfer, 0, sizeof(handle->transfer));
/* Record that we're busy. */
handle->isBusy = true;
/* Set up event mask. tx and rx are always enabled. */
handle->eventMask = eventMask | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent;
/* Ack by default. */
base->STAR = 0;
/* Clear all flags. */
LPI2C_SlaveClearStatusFlags(base, kSlaveClearFlags);
/* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
LPI2C_SlaveEnableInterrupts(base, kSlaveIrqFlags);
return kStatus_Success;
}
/*!
* brief Gets the slave transfer status during a non-blocking transfer.
* param base The LPI2C peripheral base address.
* param handle Pointer to i2c_slave_handle_t structure.
* param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not
* required.
* retval #kStatus_Success
* retval #kStatus_NoTransferInProgress
*/
status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count)
{
assert(handle);
if (!count)
{
return kStatus_InvalidArgument;
}
/* Catch when there is not an active transfer. */
if (!handle->isBusy)
{
*count = 0;
return kStatus_NoTransferInProgress;
}
/* For an active transfer, just return the count from the handle. */
*count = handle->transferredCount;
return kStatus_Success;
}
/*!
* brief Aborts the slave non-blocking transfers.
* note This API could be called at any time to stop slave for handling the bus events.
* param base The LPI2C peripheral base address.
* param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
* retval #kStatus_Success
* retval #kStatus_LPI2C_Idle
*/
void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
{
assert(handle);
/* Return idle if no transaction is in progress. */
if (handle->isBusy)
{
/* Disable LPI2C IRQ sources. */
LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags);
/* Nack by default. */
base->STAR = LPI2C_STAR_TXNACK_MASK;
/* Reset transfer info. */
memset(&handle->transfer, 0, sizeof(handle->transfer));
/* We're no longer busy. */
handle->isBusy = false;
}
}
/*!
* brief Reusable routine to handle slave interrupts.
* note This function does not need to be called unless you are reimplementing the
* non blocking API's interrupt handler routines to add special functionality.
* param base The LPI2C peripheral base address.
* param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
*/
void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
{
uint32_t flags;
lpi2c_slave_transfer_t *xfer;
/* Check for a valid handle in case of a spurious interrupt. */
if (!handle)
{
return;
}
xfer = &handle->transfer;
/* Get status flags. */
flags = LPI2C_SlaveGetStatusFlags(base);
if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag))
{
xfer->event = kLPI2C_SlaveCompletionEvent;
xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags);
if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback))
{
handle->callback(base, xfer, handle->userData);
}
return;
}
if (flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag))
{
xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent :
kLPI2C_SlaveCompletionEvent;
xfer->receivedAddress = 0;
xfer->completionStatus = kStatus_Success;
xfer->transferredCount = handle->transferredCount;
if (xfer->event == kLPI2C_SlaveCompletionEvent)
{
handle->isBusy = false;
}
if (handle->wasTransmit)
{
/* Subtract one from the transmit count to offset the fact that LPI2C asserts the */
/* tx flag before it sees the nack from the master-receiver, thus causing one more */
/* count that the master actually receives. */
--xfer->transferredCount;
handle->wasTransmit = false;
}
/* Clear the flag. */
LPI2C_SlaveClearStatusFlags(base, flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag));
/* Revert to sending an Ack by default, in case we sent a Nack for receive. */
base->STAR = 0;
if ((handle->eventMask & xfer->event) && (handle->callback))
{
handle->callback(base, xfer, handle->userData);
}
/* Clean up transfer info on completion, after the callback has been invoked. */
memset(&handle->transfer, 0, sizeof(handle->transfer));
}
if (flags & kLPI2C_SlaveAddressValidFlag)
{
xfer->event = kLPI2C_SlaveAddressMatchEvent;
xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK;
if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback))
{
handle->callback(base, xfer, handle->userData);
}
}
if (flags & kLPI2C_SlaveTransmitAckFlag)
{
xfer->event = kLPI2C_SlaveTransmitAckEvent;
if ((handle->eventMask & kLPI2C_SlaveTransmitAckEvent) && (handle->callback))
{
handle->callback(base, xfer, handle->userData);
}
}
/* Handle transmit and receive. */
if (flags & kLPI2C_SlaveTxReadyFlag)
{
handle->wasTransmit = true;
/* If we're out of data, invoke callback to get more. */
if ((!xfer->data) || (!xfer->dataSize))
{
xfer->event = kLPI2C_SlaveTransmitEvent;
if (handle->callback)
{
handle->callback(base, xfer, handle->userData);
}
/* Clear the transferred count now that we have a new buffer. */
handle->transferredCount = 0;
}
/* Transmit a byte. */
if ((xfer->data) && (xfer->dataSize))
{
base->STDR = *xfer->data++;
--xfer->dataSize;
++handle->transferredCount;
}
}
if (flags & kLPI2C_SlaveRxReadyFlag)
{
/* If we're out of room in the buffer, invoke callback to get another. */
if ((!xfer->data) || (!xfer->dataSize))
{
xfer->event = kLPI2C_SlaveReceiveEvent;
if (handle->callback)
{
handle->callback(base, xfer, handle->userData);
}
/* Clear the transferred count now that we have a new buffer. */
handle->transferredCount = 0;
}
/* Receive a byte. */
if ((xfer->data) && (xfer->dataSize))
{
*xfer->data++ = base->SRDR;
--xfer->dataSize;
++handle->transferredCount;
}
else
{
/* We don't have any room to receive more data, so send a nack. */
base->STAR = LPI2C_STAR_TXNACK_MASK;
}
}
}
/*!
* @brief Shared IRQ handler that can call both master and slave ISRs.
*
* The master and slave ISRs are called through function pointers in order to decouple
* this code from the ISR functions. Without this, the linker would always pull in both
* ISRs and every function they call, even if only the functional API was used.
*
* @param base The LPI2C peripheral base address.
* @param instance The LPI2C peripheral instance number.
*/
static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance)
{
/* Check for master IRQ. */
if ((base->MCR & LPI2C_MCR_MEN_MASK) && s_lpi2cMasterIsr)
{
/* Master mode. */
s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]);
}
/* Check for slave IRQ. */
if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr)
{
/* Slave mode. */
s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]);
}
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
#if defined(LPI2C0)
/* Implementation of LPI2C0 handler named in startup code. */
void LPI2C0_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C0, 0);
}
#endif
#if defined(LPI2C1)
/* Implementation of LPI2C1 handler named in startup code. */
void LPI2C1_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C1, 1);
}
#endif
#if defined(LPI2C2)
/* Implementation of LPI2C2 handler named in startup code. */
void LPI2C2_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C2, 2);
}
#endif
#if defined(LPI2C3)
/* Implementation of LPI2C3 handler named in startup code. */
void LPI2C3_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C3, 3);
}
#endif
#if defined(LPI2C4)
/* Implementation of LPI2C4 handler named in startup code. */
void LPI2C4_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(LPI2C4, 4);
}
#endif
#if defined(CM4_0__LPI2C)
/* Implementation of CM4_0__LPI2C handler named in startup code. */
void M4_0_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C));
}
#endif
#if defined(CM4__LPI2C)
/* Implementation of CM4__LPI2C handler named in startup code. */
void M4_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C));
}
#endif
#if defined(CM4_1__LPI2C)
/* Implementation of CM4_1__LPI2C handler named in startup code. */
void M4_1_LPI2C_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C));
}
#endif
#if defined(DMA__LPI2C0)
/* Implementation of DMA__LPI2C0 handler named in startup code. */
void DMA_I2C0_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0));
}
#endif
#if defined(DMA__LPI2C1)
/* Implementation of DMA__LPI2C1 handler named in startup code. */
void DMA_I2C1_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1));
}
#endif
#if defined(DMA__LPI2C2)
/* Implementation of DMA__LPI2C2 handler named in startup code. */
void DMA_I2C2_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2));
}
#endif
#if defined(DMA__LPI2C3)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void DMA_I2C3_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3));
}
#endif
#if defined(DMA__LPI2C4)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void DMA_I2C4_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4));
}
#endif
#if defined(ADMA__LPI2C0)
/* Implementation of DMA__LPI2C0 handler named in startup code. */
void ADMA_I2C0_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0));
}
#endif
#if defined(ADMA__LPI2C1)
/* Implementation of DMA__LPI2C1 handler named in startup code. */
void ADMA_I2C1_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1));
}
#endif
#if defined(ADMA__LPI2C2)
/* Implementation of DMA__LPI2C2 handler named in startup code. */
void ADMA_I2C2_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2));
}
#endif
#if defined(ADMA__LPI2C3)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void ADMA_I2C3_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3));
}
#endif
#if defined(ADMA__LPI2C4)
/* Implementation of DMA__LPI2C3 handler named in startup code. */
void ADMA_I2C4_INT_DriverIRQHandler(void)
{
LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4));
}
#endif
|