/******************************************************************************
*
* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* MSP432P401R Register Definitions
*
* This file includes CMSIS compliant component and register definitions
*
* For legacy components the definitions that are compatible with MSP430 code,
* are included with msp432p401r_classic.h
*
* With CMSIS definitions, the register defines have been reformatted:
* ModuleName[ModuleInstance]->RegisterName
*
* Writing to CMSIS bit fields can be done through register level
* or via bitband area access:
* - ADC14->CTL0 |= ADC14_CTL0_ENC;
* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
*
* File creation date: 2017-08-03
*
******************************************************************************/
#ifndef __MSP432P401R_H__
#define __MSP432P401R_H__
/* Use standard integer types with explicit width */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __MSP432_HEADER_VERSION__ 3202
/* Remap MSP432 intrinsics to ARM equivalents */
#include "msp_compatibility.h"
/******************************************************************************
* include MSP430 legacy definitions to make porting of code from MSP430 *
* code base easier *
* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in *
* your project to omit including the classic defines *
******************************************************************************/
#ifndef NO_MSP_CLASSIC_DEFINES
#include "msp432p401r_classic.h"
#endif
#ifndef __CMSIS_CONFIG__
#define __CMSIS_CONFIG__
/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions
This file defines all structures and symbols for MSP432P401R:
- components and registers
- peripheral base address
- peripheral ID
- Peripheral definitions
@{
*/
/******************************************************************************
* Processor and Core Peripherals *
******************************************************************************/
/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions
Configuration of the Cortex-M4 Processor and Core Peripherals
@{
*/
/******************************************************************************
* CMSIS-compatible Interrupt Number Definition *
******************************************************************************/
typedef enum IRQn
{
/* Cortex-M4 Processor Exceptions Numbers */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* Peripheral Exceptions Numbers */
PSS_IRQn = 0, /* 16 PSS Interrupt */
CS_IRQn = 1, /* 17 CS Interrupt */
PCM_IRQn = 2, /* 18 PCM Interrupt */
WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */
FPU_IRQn = 4, /* 20 FPU Interrupt */
FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/
COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */
COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */
TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */
TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */
TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */
TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */
TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */
TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */
TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */
TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */
EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */
EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */
EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */
EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */
EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */
EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */
EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */
EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */
ADC14_IRQn = 24, /* 40 ADC14 Interrupt */
T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */
T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */
T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */
AES256_IRQn = 28, /* 44 AES256 Interrupt */
RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */
DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */
DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */
DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */
DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */
DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */
PORT1_IRQn = 35, /* 51 Port1 Interrupt */
PORT2_IRQn = 36, /* 52 Port2 Interrupt */
PORT3_IRQn = 37, /* 53 Port3 Interrupt */
PORT4_IRQn = 38, /* 54 Port4 Interrupt */
PORT5_IRQn = 39, /* 55 Port5 Interrupt */
PORT6_IRQn = 40 /* 56 Port6 Interrupt */
} IRQn_Type;
/******************************************************************************
* Processor and Core Peripheral Section *
******************************************************************************/
#define __CM4_REV 0x0001 /* Core revision r0p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /* FPU present or not */
/******************************************************************************
* Available Peripherals *
******************************************************************************/
#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */
#define __MCU_HAS_AES256__ /*!< Module AES256 is available */
#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */
#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */
#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */
#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */
#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */
#define __MCU_HAS_CS__ /*!< Module CS is available */
#define __MCU_HAS_DIO__ /*!< Module DIO is available */
#define __MCU_HAS_DMA__ /*!< Module DMA is available */
#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */
#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */
#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */
#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */
#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */
#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */
#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */
#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */
#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */
#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */
#define __MCU_HAS_PCM__ /*!< Module PCM is available */
#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */
#define __MCU_HAS_PSS__ /*!< Module PSS is available */
#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */
#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */
#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */
#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */
#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */
#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */
#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */
#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */
#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */
#define __MCU_HAS_TLV__ /*!< Module TLV is available */
#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */
/* Definitions to show that specific ports are available */
#define __MSP432_HAS_PORTA_R__
#define __MSP432_HAS_PORTB_R__
#define __MSP432_HAS_PORTC_R__
#define __MSP432_HAS_PORTD_R__
#define __MSP432_HAS_PORTE_R__
#define __MSP432_HAS_PORTJ_R__
#define __MSP432_HAS_PORT1_R__
#define __MSP432_HAS_PORT2_R__
#define __MSP432_HAS_PORT3_R__
#define __MSP432_HAS_PORT4_R__
#define __MSP432_HAS_PORT5_R__
#define __MSP432_HAS_PORT6_R__
#define __MSP432_HAS_PORT7_R__
#define __MSP432_HAS_PORT8_R__
#define __MSP432_HAS_PORT9_R__
#define __MSP432_HAS_PORT10_R__
/*@}*/ /* end of group MSP432P401R_CMSIS */
/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
#ifdef __TI_ARM__
/* disable the TI ULP advisor check for the core header file definitions */
#pragma diag_push
#pragma CHECK_ULP("none")
#include "core_cm4.h"
#pragma diag_pop
#else
#include "core_cm4.h"
#endif
/* System Header */
#include "system_msp432p401r.h"
/******************************************************************************
* Definition of standard bits *
******************************************************************************/
#define BIT0 (uint16_t)(0x0001)
#define BIT1 (uint16_t)(0x0002)
#define BIT2 (uint16_t)(0x0004)
#define BIT3 (uint16_t)(0x0008)
#define BIT4 (uint16_t)(0x0010)
#define BIT5 (uint16_t)(0x0020)
#define BIT6 (uint16_t)(0x0040)
#define BIT7 (uint16_t)(0x0080)
#define BIT8 (uint16_t)(0x0100)
#define BIT9 (uint16_t)(0x0200)
#define BITA (uint16_t)(0x0400)
#define BITB (uint16_t)(0x0800)
#define BITC (uint16_t)(0x1000)
#define BITD (uint16_t)(0x2000)
#define BITE (uint16_t)(0x4000)
#define BITF (uint16_t)(0x8000)
/******************************************************************************
* Device and peripheral memory map *
******************************************************************************/
/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping
@{
*/
#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */
#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */
#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */
#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */
#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */
#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */
#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */
#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */
#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */
#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */
#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */
#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */
#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */
#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */
#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */
#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */
#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */
#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */
#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */
#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */
#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */
#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */
#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */
#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */
#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */
#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */
#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */
#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */
#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */
#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */
#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */
#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */
#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */
#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */
#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */
#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */
#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */
#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */
#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */
#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */
#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */
#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */
#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */
#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */
#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */
/*@}*/ /* end of group MSP432P401R_MemoryMap */
/******************************************************************************
* Definitions for bit band access *
******************************************************************************/
#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000))
#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
/* SRAM allows 32 bit bit band access */
#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4)))
/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
/******************************************************************************
* Peripheral register definitions *
******************************************************************************/
/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals
MSP432P401R Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************
* ADC14 Registers
******************************************************************************/
/** @addtogroup ADC14 MSP432P401R (ADC14)
@{
*/
typedef struct {
__IO uint32_t CTL0; /*!< Control 0 Register */
__IO uint32_t CTL1; /*!< Control 1 Register */
__IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */
__IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */
__IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */
__IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */
__IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */
__IO uint32_t MEM[32]; /*!< Conversion Memory Register */
uint32_t RESERVED0[9];
__IO uint32_t IER0; /*!< Interrupt Enable 0 Register */
__IO uint32_t IER1; /*!< Interrupt Enable 1 Register */
__I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */
__I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */
__O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */
__IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */
__IO uint32_t IV; /*!< Interrupt Vector Register */
} ADC14_Type;
/*@}*/ /* end of group ADC14 */
/******************************************************************************
* AES256 Registers
******************************************************************************/
/** @addtogroup AES256 MSP432P401R (AES256)
@{
*/
typedef struct {
__IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */
__IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */
__IO uint16_t STAT; /*!< AES Accelerator Status Register */
__O uint16_t KEY; /*!< AES Accelerator Key Register */
__O uint16_t DIN; /*!< AES Accelerator Data In Register */
__O uint16_t DOUT; /*!< AES Accelerator Data Out Register */
__O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */
__O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */
} AES256_Type;
/*@}*/ /* end of group AES256 */
/******************************************************************************
* CAPTIO Registers
******************************************************************************/
/** @addtogroup CAPTIO MSP432P401R (CAPTIO)
@{
*/
typedef struct {
uint16_t RESERVED0[7];
__IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */
} CAPTIO_Type;
/*@}*/ /* end of group CAPTIO */
/******************************************************************************
* COMP_E Registers
******************************************************************************/
/** @addtogroup COMP_E MSP432P401R (COMP_E)
@{
*/
typedef struct {
__IO uint16_t CTL0; /*!< Comparator Control Register 0 */
__IO uint16_t CTL1; /*!< Comparator Control Register 1 */
__IO uint16_t CTL2; /*!< Comparator Control Register 2 */
__IO uint16_t CTL3; /*!< Comparator Control Register 3 */
uint16_t RESERVED0[2];
__IO uint16_t INT; /*!< Comparator Interrupt Control Register */
__I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */
} COMP_E_Type;
/*@}*/ /* end of group COMP_E */
/******************************************************************************
* CRC32 Registers
******************************************************************************/
/** @addtogroup CRC32 MSP432P401R (CRC32)
@{
*/
typedef struct {
__IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */
uint16_t RESERVED0;
__IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */
uint16_t RESERVED1;
__IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */
__IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */
__IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */
__IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */
__IO uint16_t DI16; /*!< Data Input for CRC16 computation */
uint16_t RESERVED2;
__IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */
uint16_t RESERVED3;
__IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */
uint16_t RESERVED4[2];
__IO uint16_t RESR16; /*!< CRC16 Result Reverse */
} CRC32_Type;
/*@}*/ /* end of group CRC32 */
/******************************************************************************
* CS Registers
******************************************************************************/
/** @addtogroup CS MSP432P401R (CS)
@{
*/
typedef struct {
__IO uint32_t KEY; /*!< Key Register */
__IO uint32_t CTL0; /*!< Control 0 Register */
__IO uint32_t CTL1; /*!< Control 1 Register */
__IO uint32_t CTL2; /*!< Control 2 Register */
__IO uint32_t CTL3; /*!< Control 3 Register */
uint32_t RESERVED0[7];
__IO uint32_t CLKEN; /*!< Clock Enable Register */
__I uint32_t STAT; /*!< Status Register */
uint32_t RESERVED1[2];
__IO uint32_t IE; /*!< Interrupt Enable Register */
uint32_t RESERVED2;
__I uint32_t IFG; /*!< Interrupt Flag Register */
uint32_t RESERVED3;
__O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */
uint32_t RESERVED4;
__O uint32_t SETIFG; /*!< Set Interrupt Flag Register */
uint32_t RESERVED5;
__IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */
__IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */
} CS_Type;
/*@}*/ /* end of group CS */
/******************************************************************************
* DIO Registers
******************************************************************************/
/** @addtogroup DIO MSP432P401R (DIO)
@{
*/
typedef struct {
union {
__I uint16_t IN; /*!< Port Pair Input */
struct {
__I uint8_t IN_L; /*!< Low Port Input */
__I uint8_t IN_H; /*!< High Port Input */
};
};
union {
__IO uint16_t OUT; /*!< Port Pair Output */
struct {
__IO uint8_t OUT_L; /*!< Low Port Output */
__IO uint8_t OUT_H; /*!< High Port Output */
};
};
union {
__IO uint16_t DIR; /*!< Port Pair Direction */
struct {
__IO uint8_t DIR_L; /*!< Low Port Direction */
__IO uint8_t DIR_H; /*!< High Port Direction */
};
};
union {
__IO uint16_t REN; /*!< Port Pair Resistor Enable */
struct {
__IO uint8_t REN_L; /*!< Low Port Resistor Enable */
__IO uint8_t REN_H; /*!< High Port Resistor Enable */
};
};
union {
__IO uint16_t DS; /*!< Port Pair Drive Strength */
struct {
__IO uint8_t DS_L; /*!< Low Port Drive Strength */
__IO uint8_t DS_H; /*!< High Port Drive Strength */
};
};
union {
__IO uint16_t SEL0; /*!< Port Pair Select 0 */
struct {
__IO uint8_t SEL0_L; /*!< Low Port Select 0 */
__IO uint8_t SEL0_H; /*!< High Port Select 0 */
};
};
union {
__IO uint16_t SEL1; /*!< Port Pair Select 1 */
struct {
__IO uint8_t SEL1_L; /*!< Low Port Select 1 */
__IO uint8_t SEL1_H; /*!< High Port Select 1 */
};
};
__I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */
uint16_t RESERVED0[3];
union {
__IO uint16_t SELC; /*!< Port Pair Complement Select */
struct {
__IO uint8_t SELC_L; /*!< Low Port Complement Select */
__IO uint8_t SELC_H; /*!< High Port Complement Select */
};
};
union {
__IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */
struct {
__IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */
__IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */
};
};
union {
__IO uint16_t IE; /*!< Port Pair Interrupt Enable */
struct {
__IO uint8_t IE_L; /*!< Low Port Interrupt Enable */
__IO uint8_t IE_H; /*!< High Port Interrupt Enable */
};
};
union {
__IO uint16_t IFG; /*!< Port Pair Interrupt Flag */
struct {
__IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */
__IO uint8_t IFG_H; /*!< High Port Interrupt Flag */
};
};
__I uint16_t IV_H; /*!< High Port Interrupt Vector Value */
} DIO_PORT_Interruptable_Type;
typedef struct {
union {
__I uint16_t IN; /*!< Port Pair Input */
struct {
__I uint8_t IN_L; /*!< Low Port Input */
__I uint8_t IN_H; /*!< High Port Input */
};
};
union {
__IO uint16_t OUT; /*!< Port Pair Output */
struct {