Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 | # Kconfig.dw - DesignWare SPI driver configuration options # # # Copyright (c) 2015-2016 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 # config HAS_SPI_DW bool help Signifies whether DesignWare SPI compatible HW is available menuconfig SPI_DW bool "Designware SPI controller driver" depends on HAS_SPI_DW help Enable support for Designware's SPI controllers. if SPI_DW config SPI_DW_ARC_AUX_REGS bool "Registers are part of ARC auxiliary registers" depends on ARC default y help SPI IP block registers are part of user extended auxiliary registers and thus their access is different than memory mapped registers. config SPI_DW_FIFO_DEPTH int "RX and TX FIFO Depth" help Corresponds to the SSI_TX_FIFO_DEPTH and SSI_RX_FIFO_DEPTH of the DesignWare Synchronous Serial Interface. Depth ranges from 2-256. if SPI_0 config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE bool "Single interrupt line for all interrupts" default y help Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. config SPI_DW_PORT_0_CLOCK_GATE bool "Enable clock gating" depends on CLOCK_CONTROL if SPI_DW_PORT_0_CLOCK_GATE config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME string config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" endif # SPI_DW_PORT_0_CLOCK_GATE endif # SPI_0 if SPI_1 config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE bool "Single interrupt line for all interrupts" default y config SPI_DW_PORT_1_CLOCK_GATE bool "Enable clock gating" depends on CLOCK_CONTROL if SPI_DW_PORT_1_CLOCK_GATE config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME string config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" endif # SPI_DW_PORT_1_CLOCK_GATE endif # SPI_1 if SPI_2 config SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE bool "Single interrupt line for all interrupts" default y help Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. config SPI_DW_PORT_2_CLOCK_GATE bool "Enable clock gating" depends on CLOCK_CONTROL if SPI_DW_PORT_2_CLOCK_GATE config SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME string default "" config SPI_DW_PORT_2_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" endif # SPI_DW_PORT_2_CLOCK_GATE endif # SPI_2 if SPI_3 config SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE bool "Single interrupt line for all interrupts" default y help Only one line is used to trigger interrupts: RX, TX and ERROR interrupt go all through that line, undifferentiated. config SPI_DW_PORT_3_CLOCK_GATE bool "Enable clock gating" depends on CLOCK_CONTROL if SPI_DW_PORT_3_CLOCK_GATE config SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME string default "" config SPI_DW_PORT_3_CLOCK_GATE_SUBSYS int "Clock controller's subsystem" endif # SPI_DW_PORT_3_CLOCK_GATE endif # SPI_3 endif # SPI_DW |