Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 | /**
******************************************************************************
* @file stm32f2xx_ll_rcc.h
* @author MCD Application Team
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F2xx_LL_RCC_H
#define __STM32F2xx_LL_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx.h"
/** @addtogroup STM32F2xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup RCC_LL_Private_Variables RCC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Private_Macros RCC Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
* @{
*/
/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
* @{
*/
/**
* @brief RCC Clocks Frequency Structure
*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
} LL_RCC_ClocksTypeDef;
/**
* @}
*/
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
* @{
*/
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
* @brief Defines used to adapt values of different oscillators
* @note These values could be modified in the user environment according to
* HW set-up.
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
#endif /* HSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
#endif /* EXTERNAL_CLOCK_VALUE */
/**
* @}
*/
/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_RCC_WriteReg function
* @{
*/
#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
/**
* @}
*/
/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RCC_ReadReg function
* @{
*/
#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
/**
* @}
*/
/** @defgroup RCC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
* @{
*/
#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
* @{
*/
#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
* @{
*/
#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
* @{
*/
#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
* @{
*/
#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
* @{
*/
#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
* @{
*/
#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
* @{
*/
#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
* @{
*/
#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source
* @{
*/
#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor
* @{
*/
#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 2 */
#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 3 */
#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 4 */
#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 5 */
#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 6 */
#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 7 */
#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 8 */
#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 9 */
#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 10 */
#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 11 */
#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 12 */
#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 13 */
#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 14 */
#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 15 */
#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 16 */
#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 17 */
#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 18 */
#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 19 */
#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 20 */
#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 21 */
#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 22 */
#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 23 */
#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 24 */
#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 25 */
#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 26 */
#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 27 */
#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 28 */
#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 29 */
#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 30 */
#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 31 */
#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL and PLLI2S division factor by 32 */
#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 33 */
#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 34 */
#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 35 */
#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 36 */
#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 37 */
#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 38 */
#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 39 */
#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 40 */
#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 41 */
#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 42 */
#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 43 */
#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 44 */
#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 45 */
#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 46 */
#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 47 */
#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL and PLLI2S division factor by 48 */
#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 49 */
#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 50 */
#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 51 */
#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 52 */
#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 53 */
#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 54 */
#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 55 */
#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL and PLLI2S division factor by 56 */
#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 57 */
#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 58 */
#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 59 */
#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL and PLLI2S division factor by 60 */
#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 61 */
#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL and PLLI2S division factor by 62 */
#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL and PLLI2S division factor by 63 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
* @{
*/
#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
* @{
*/
#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
* @{
*/
#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
* @{
*/
#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
* @{
*/
/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RCC register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
/**
* @brief Read a value in RCC register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
/**
* @}
*/
/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
* @{
*/
/**
* @brief Helper macro to calculate the PLLCLK frequency on system domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
* @param __PLLN__ Between 192 and 432
* @param __PLLP__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_8
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
/**
* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
* @param __PLLN__ Between 192 and 432
* @param __PLLQ__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_3
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_5
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_7
* @arg @ref LL_RCC_PLLQ_DIV_8
* @arg @ref LL_RCC_PLLQ_DIV_9
* @arg @ref LL_RCC_PLLQ_DIV_10
* @arg @ref LL_RCC_PLLQ_DIV_11
* @arg @ref LL_RCC_PLLQ_DIV_12
* @arg @ref LL_RCC_PLLQ_DIV_13
* @arg @ref LL_RCC_PLLQ_DIV_14
* @arg @ref LL_RCC_PLLQ_DIV_15
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
/**
* @retval PLLI2S clock frequency (in Hz)
*/
/**
* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @param __PLLI2SN__ Between 192 and 432
* @param __PLLI2SR__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLI2SR_DIV_2
* @arg @ref LL_RCC_PLLI2SR_DIV_3
* @arg @ref LL_RCC_PLLI2SR_DIV_4
* @arg @ref LL_RCC_PLLI2SR_DIV_5
* @arg @ref LL_RCC_PLLI2SR_DIV_6
* @arg @ref LL_RCC_PLLI2SR_DIV_7
* @retval PLLI2S clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
/**
* @brief Helper macro to calculate the HCLK frequency
* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
* @param __AHBPRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval HCLK clock frequency (in Hz)
*/
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
/**
* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB1PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval PCLK1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
/**
* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB2PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval PCLK2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
* @{
*/
/** @defgroup RCC_LL_EF_HSE HSE
* @{
*/
/**
* @brief Enable the Clock Security System.
* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
{
SET_BIT(RCC->CR, RCC_CR_CSSON);
}
/**
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Disable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_HSI HSI
* @{
*/
/**
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Disable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
}
/**
* @brief Get HSI Calibration value
* @note When HSITRIM is written, HSICAL is updated with the sum of
* HSITRIM and the factory trim value
* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
{
return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
}
/**
* @brief Set HSI Calibration trimming
* @note user-programmable trimming value that is added to the HSICAL
* @note Default value is 16, which, when added to the HSICAL value,
* should trim the HSI to 16 MHz +/- 1 %
* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 31
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
{
MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
}
/**
* @brief Get HSI Calibration trimming
* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
* @retval Between Min_Data = 0 and Max_Data = 31
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
{
return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSE LSE
* @{
*/
/**
* @brief Enable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Disable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Enable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Disable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Check if LSE oscillator Ready
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSI LSI
* @{
*/
/**
* @brief Enable LSI Oscillator
* @rmtoll CSR LSION LL_RCC_LSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
{
SET_BIT(RCC->CSR, RCC_CSR_LSION);
}
/**
* @brief Disable LSI Oscillator
* @rmtoll CSR LSION LL_RCC_LSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
{
CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
}
/**
* @brief Check if LSI is Ready
* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_System System
* @{
*/
/**
* @brief Configure the system clock source
* @rmtoll CFGR SW LL_RCC_SetSysClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
}
/**
* @brief Get the system clock source
* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
}
/**
* @brief Set AHB prescaler
* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
}
/**
* @brief Set APB1 prescaler
* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
}
/**
* @brief Set APB2 prescaler
* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
}
/**
* @brief Get AHB prescaler
* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
*/
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
}
/**
* @brief Get APB1 prescaler
* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
}
/**
* @brief Get APB2 prescaler
* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_MCO MCO
* @{
*/
/**
* @brief Configure MCOx
* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
* CFGR MCO1PRE LL_RCC_ConfigMCO\n
* CFGR MCO2 LL_RCC_ConfigMCO\n
* CFGR MCO2PRE LL_RCC_ConfigMCO
* @param MCOxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1SOURCE_HSI
* @arg @ref LL_RCC_MCO1SOURCE_LSE
* @arg @ref LL_RCC_MCO1SOURCE_HSE
* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
* @arg @ref LL_RCC_MCO2SOURCE_HSE
* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
* @param MCOxPrescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1_DIV_1
* @arg @ref LL_RCC_MCO1_DIV_2
* @arg @ref LL_RCC_MCO1_DIV_3
* @arg @ref LL_RCC_MCO1_DIV_4
* @arg @ref LL_RCC_MCO1_DIV_5
* @arg @ref LL_RCC_MCO2_DIV_1
* @arg @ref LL_RCC_MCO2_DIV_2
* @arg @ref LL_RCC_MCO2_DIV_3
* @arg @ref LL_RCC_MCO2_DIV_4
* @arg @ref LL_RCC_MCO2_DIV_5
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
{
MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
* @{
*/
/**
* @brief Configure I2S clock source
* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
}
/**
* @brief Get I2S Clock Source
* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
* @param I2Sx This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
{
return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_RTC RTC
* @{
*/
/**
* @brief Set RTC Clock Source
* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
* set). The BDRST bit can be used to reset them.
* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
}
/**
* @brief Get RTC Clock Source
* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
}
/**
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Disable RTC
* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableRTC(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Check if RTC has been enabled or not
* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
{
return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
}
/**
* @brief Force the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @brief Release the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @brief Set HSE Prescalers for RTC Clock
* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_RTC_NOCLOCK
* @arg @ref LL_RCC_RTC_HSE_DIV_2
* @arg @ref LL_RCC_RTC_HSE_DIV_3
* @arg @ref LL_RCC_RTC_HSE_DIV_4
* @arg @ref LL_RCC_RTC_HSE_DIV_5
* @arg @ref LL_RCC_RTC_HSE_DIV_6
* @arg @ref LL_RCC_RTC_HSE_DIV_7
* @arg @ref LL_RCC_RTC_HSE_DIV_8
* @arg @ref LL_RCC_RTC_HSE_DIV_9
* @arg @ref LL_RCC_RTC_HSE_DIV_10
* @arg @ref LL_RCC_RTC_HSE_DIV_11
* @arg @ref LL_RCC_RTC_HSE_DIV_12
* @arg @ref LL_RCC_RTC_HSE_DIV_13
* @arg @ref LL_RCC_RTC_HSE_DIV_14
* @arg @ref LL_RCC_RTC_HSE_DIV_15
* @arg @ref LL_RCC_RTC_HSE_DIV_16
* @arg @ref LL_RCC_RTC_HSE_DIV_17
* @arg @ref LL_RCC_RTC_HSE_DIV_18
* @arg @ref LL_RCC_RTC_HSE_DIV_19
* @arg @ref LL_RCC_RTC_HSE_DIV_20
* @arg @ref LL_RCC_RTC_HSE_DIV_21
* @arg @ref LL_RCC_RTC_HSE_DIV_22
* @arg @ref LL_RCC_RTC_HSE_DIV_23
* @arg @ref LL_RCC_RTC_HSE_DIV_24
* @arg @ref LL_RCC_RTC_HSE_DIV_25
* @arg @ref LL_RCC_RTC_HSE_DIV_26
* @arg @ref LL_RCC_RTC_HSE_DIV_27
* @arg @ref LL_RCC_RTC_HSE_DIV_28
* @arg @ref LL_RCC_RTC_HSE_DIV_29
* @arg @ref LL_RCC_RTC_HSE_DIV_30
* @arg @ref LL_RCC_RTC_HSE_DIV_31
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
}
/**
* @brief Get HSE Prescalers for RTC Clock
* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RTC_NOCLOCK
* @arg @ref LL_RCC_RTC_HSE_DIV_2
* @arg @ref LL_RCC_RTC_HSE_DIV_3
* @arg @ref LL_RCC_RTC_HSE_DIV_4
* @arg @ref LL_RCC_RTC_HSE_DIV_5
* @arg @ref LL_RCC_RTC_HSE_DIV_6
* @arg @ref LL_RCC_RTC_HSE_DIV_7
* @arg @ref LL_RCC_RTC_HSE_DIV_8
* @arg @ref LL_RCC_RTC_HSE_DIV_9
* @arg @ref LL_RCC_RTC_HSE_DIV_10
* @arg @ref LL_RCC_RTC_HSE_DIV_11
* @arg @ref LL_RCC_RTC_HSE_DIV_12
* @arg @ref LL_RCC_RTC_HSE_DIV_13
* @arg @ref LL_RCC_RTC_HSE_DIV_14
* @arg @ref LL_RCC_RTC_HSE_DIV_15
* @arg @ref LL_RCC_RTC_HSE_DIV_16
* @arg @ref LL_RCC_RTC_HSE_DIV_17
* @arg @ref LL_RCC_RTC_HSE_DIV_18
* @arg @ref LL_RCC_RTC_HSE_DIV_19
* @arg @ref LL_RCC_RTC_HSE_DIV_20
* @arg @ref LL_RCC_RTC_HSE_DIV_21
* @arg @ref LL_RCC_RTC_HSE_DIV_22
* @arg @ref LL_RCC_RTC_HSE_DIV_23
* @arg @ref LL_RCC_RTC_HSE_DIV_24
* @arg @ref LL_RCC_RTC_HSE_DIV_25
* @arg @ref LL_RCC_RTC_HSE_DIV_26
* @arg @ref LL_RCC_RTC_HSE_DIV_27
* @arg @ref LL_RCC_RTC_HSE_DIV_28
* @arg @ref LL_RCC_RTC_HSE_DIV_29
* @arg @ref LL_RCC_RTC_HSE_DIV_30
* @arg @ref LL_RCC_RTC_HSE_DIV_31
*/
__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLL PLL
* @{
*/
/**
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLLON);
}
/**
* @brief Disable PLL
* @note Cannot be disabled if the PLL clock is used as the system clock
* @rmtoll CR PLLON LL_RCC_PLL_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
}
/**
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
}
/**
* @brief Configure PLL used for SYSCLK Domain
* @note PLL Source and PLLM Divider can be written only when PLL,
* PLLI2S are disabled
* @note PLLN/PLLP can be written only when PLL is disabled
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
* @param PLLN Between 192 and 432
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
}
/**
* @brief Configure PLL used for 48Mhz domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
* PLLI2S are disabled
* @note PLLN/PLLQ can be written only when PLL is disabled
* @note This can be selected for USB, RNG, SDIO
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
* @param PLLN Between 192 and 432
* @param PLLQ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_3
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_5
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_7
* @arg @ref LL_RCC_PLLQ_DIV_8
* @arg @ref LL_RCC_PLLQ_DIV_9
* @arg @ref LL_RCC_PLLQ_DIV_10
* @arg @ref LL_RCC_PLLQ_DIV_11
* @arg @ref LL_RCC_PLLQ_DIV_12
* @arg @ref LL_RCC_PLLQ_DIV_13
* @arg @ref LL_RCC_PLLQ_DIV_14
* @arg @ref LL_RCC_PLLQ_DIV_15
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
}
/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between 192 and 432
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
}
/**
* @brief Get Main PLL division factor for PLLP
* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_8
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
}
/**
* @brief Get Main PLL division factor for PLLQ
* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_3
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_5
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_7
* @arg @ref LL_RCC_PLLQ_DIV_8
* @arg @ref LL_RCC_PLLQ_DIV_9
* @arg @ref LL_RCC_PLLQ_DIV_10
* @arg @ref LL_RCC_PLLQ_DIV_11
* @arg @ref LL_RCC_PLLQ_DIV_12
* @arg @ref LL_RCC_PLLQ_DIV_13
* @arg @ref LL_RCC_PLLQ_DIV_14
* @arg @ref LL_RCC_PLLQ_DIV_15
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
}
/**
* @brief Get the oscillator used as PLL clock source.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
}
/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
}
/**
* @brief Configure Spread Spectrum used for PLL
* @note These bits must be written before enabling PLL
* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
* @param Mod Between Min_Data=0 and Max_Data=8191
* @param Inc Between Min_Data=0 and Max_Data=32767
* @param Sel This parameter can be one of the following values:
* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
{
MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
}
/**
* @brief Get Spread Spectrum Modulation Period for PLL
* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
* @retval Between Min_Data=0 and Max_Data=8191
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
{
return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
}
/**
* @brief Get Spread Spectrum Incrementation Step for PLL
* @note Must be written before enabling PLL
* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
* @retval Between Min_Data=0 and Max_Data=32767
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
{
return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
}
/**
* @brief Get Spread Spectrum Selection for PLL
* @note Must be written before enabling PLL
* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
{
return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
}
/**
* @brief Enable Spread Spectrum for PLL.
* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
{
SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
}
/**
* @brief Disable Spread Spectrum for PLL.
* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
{
CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
* @{
*/
/**
* @brief Enable PLLI2S
* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
}
/**
* @brief Disable PLLI2S
* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
}
/**
* @brief Check if PLLI2S Ready
* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
{
return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
}
/**
* @brief Configure PLLI2S used for I2S1 domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
* PLLI2S are disabled
* @note PLLN/PLLR can be written only when PLLI2S is disabled
* @note This can be selected for I2S
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @arg @ref LL_RCC_PLLM_DIV_17
* @arg @ref LL_RCC_PLLM_DIV_18
* @arg @ref LL_RCC_PLLM_DIV_19
* @arg @ref LL_RCC_PLLM_DIV_20
* @arg @ref LL_RCC_PLLM_DIV_21
* @arg @ref LL_RCC_PLLM_DIV_22
* @arg @ref LL_RCC_PLLM_DIV_23
* @arg @ref LL_RCC_PLLM_DIV_24
* @arg @ref LL_RCC_PLLM_DIV_25
* @arg @ref LL_RCC_PLLM_DIV_26
* @arg @ref LL_RCC_PLLM_DIV_27
* @arg @ref LL_RCC_PLLM_DIV_28
* @arg @ref LL_RCC_PLLM_DIV_29
* @arg @ref LL_RCC_PLLM_DIV_30
* @arg @ref LL_RCC_PLLM_DIV_31
* @arg @ref LL_RCC_PLLM_DIV_32
* @arg @ref LL_RCC_PLLM_DIV_33
* @arg @ref LL_RCC_PLLM_DIV_34
* @arg @ref LL_RCC_PLLM_DIV_35
* @arg @ref LL_RCC_PLLM_DIV_36
* @arg @ref LL_RCC_PLLM_DIV_37
* @arg @ref LL_RCC_PLLM_DIV_38
* @arg @ref LL_RCC_PLLM_DIV_39
* @arg @ref LL_RCC_PLLM_DIV_40
* @arg @ref LL_RCC_PLLM_DIV_41
* @arg @ref LL_RCC_PLLM_DIV_42
* @arg @ref LL_RCC_PLLM_DIV_43
* @arg @ref LL_RCC_PLLM_DIV_44
* @arg @ref LL_RCC_PLLM_DIV_45
* @arg @ref LL_RCC_PLLM_DIV_46
* @arg @ref LL_RCC_PLLM_DIV_47
* @arg @ref LL_RCC_PLLM_DIV_48
* @arg @ref LL_RCC_PLLM_DIV_49
* @arg @ref LL_RCC_PLLM_DIV_50
* @arg @ref LL_RCC_PLLM_DIV_51
* @arg @ref LL_RCC_PLLM_DIV_52
* @arg @ref LL_RCC_PLLM_DIV_53
* @arg @ref LL_RCC_PLLM_DIV_54
* @arg @ref LL_RCC_PLLM_DIV_55
* @arg @ref LL_RCC_PLLM_DIV_56
* @arg @ref LL_RCC_PLLM_DIV_57
* @arg @ref LL_RCC_PLLM_DIV_58
* @arg @ref LL_RCC_PLLM_DIV_59
* @arg @ref LL_RCC_PLLM_DIV_60
* @arg @ref LL_RCC_PLLM_DIV_61
* @arg @ref LL_RCC_PLLM_DIV_62
* @arg @ref LL_RCC_PLLM_DIV_63
* @param PLLN Between 192 and 432
* @param PLLR This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLI2SR_DIV_2
* @arg @ref LL_RCC_PLLI2SR_DIV_3
* @arg @ref LL_RCC_PLLI2SR_DIV_4
* @arg @ref LL_RCC_PLLI2SR_DIV_5
* @arg @ref LL_RCC_PLLI2SR_DIV_6
* @arg @ref LL_RCC_PLLI2SR_DIV_7
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
}
/**
* @brief Get I2SPLL multiplication factor for VCO
* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
* @retval Between 192 and 432
*/
__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
{
return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
}
/**
* @brief Get I2SPLL division factor for PLLI2SR
* @note used for PLLI2SCLK (I2S clock)
* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLI2SR_DIV_2
* @arg @ref LL_RCC_PLLI2SR_DIV_3
* @arg @ref LL_RCC_PLLI2SR_DIV_4
* @arg @ref LL_RCC_PLLI2SR_DIV_5
* @arg @ref LL_RCC_PLLI2SR_DIV_6
* @arg @ref LL_RCC_PLLI2SR_DIV_7
*/
__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
{
return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Clear LSI ready interrupt flag
* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
}
/**
* @brief Clear LSE ready interrupt flag
* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
}
/**
* @brief Clear HSI ready interrupt flag
* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
}
/**
* @brief Clear HSE ready interrupt flag
* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
}
/**
* @brief Clear PLL ready interrupt flag
* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
}
/**
* @brief Clear PLLI2S ready interrupt flag
* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
}
/**
* @brief Clear Clock security system interrupt flag
* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
{
SET_BIT(RCC->CIR, RCC_CIR_CSSC);
}
/**
* @brief Check if LSI ready interrupt occurred or not
* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
}
/**
* @brief Check if LSE ready interrupt occurred or not
* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
}
/**
* @brief Check if HSI ready interrupt occurred or not
* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
}
/**
* @brief Check if HSE ready interrupt occurred or not
* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
}
/**
* @brief Check if PLL ready interrupt occurred or not
* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
}
/**
* @brief Check if PLLI2S ready interrupt occurred or not
* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
}
/**
* @brief Check if Clock security system interrupt occurred or not
* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
}
/**
* @brief Check if RCC flag Independent Watchdog reset is set or not.
* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
}
/**
* @brief Check if RCC flag Low Power reset is set or not.
* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
}
/**
* @brief Check if RCC flag Pin reset is set or not.
* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
}
/**
* @brief Check if RCC flag POR/PDR reset is set or not.
* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
}
/**
* @brief Check if RCC flag Software reset is set or not.
* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
}
/**
* @brief Check if RCC flag Window Watchdog reset is set or not.
* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
}
/**
* @brief Check if RCC flag BOR reset is set or not.
* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
{
return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
}
/**
* @brief Set RMVF bit to clear the reset flags.
* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
{
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_IT_Management IT Management
* @{
*/
/**
* @brief Enable LSI ready interrupt
* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
}
/**
* @brief Enable LSE ready interrupt
* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
}
/**
* @brief Enable HSI ready interrupt
* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
}
/**
* @brief Enable HSE ready interrupt
* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
}
/**
* @brief Enable PLL ready interrupt
* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
}
/**
* @brief Enable PLLI2S ready interrupt
* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
{
SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
}
/**
* @brief Disable LSI ready interrupt
* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
}
/**
* @brief Disable LSE ready interrupt
* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
}
/**
* @brief Disable HSI ready interrupt
* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
}
/**
* @brief Disable HSE ready interrupt
* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
}
/**
* @brief Disable PLL ready interrupt
* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
}
/**
* @brief Disable PLLI2S ready interrupt
* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
{
CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
}
/**
* @brief Checks if LSI ready interrupt source is enabled or disabled.
* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
}
/**
* @brief Checks if LSE ready interrupt source is enabled or disabled.
* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
}
/**
* @brief Checks if HSI ready interrupt source is enabled or disabled.
* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
}
/**
* @brief Checks if HSE ready interrupt source is enabled or disabled.
* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
}
/**
* @brief Checks if PLL ready interrupt source is enabled or disabled.
* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
}
/**
* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
{
return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_RCC_DeInit(void);
/**
* @}
*/
/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
* @{
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F2xx_LL_RCC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|