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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 | /* ieee802154_kw41z.c - NXP KW41Z driver */ /* * Copyright (c) 2017 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ #define LOG_MODULE_NAME ieee802154_kw41z #define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL #include <logging/log.h> LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include <zephyr.h> #include <kernel.h> #include <device.h> #include <init.h> #include <irq.h> #include <net/ieee802154_radio.h> #include <net/net_if.h> #include <net/net_pkt.h> #include <misc/byteorder.h> #include <random/rand32.h> #include "fsl_xcvr.h" #if defined(CONFIG_NET_L2_OPENTHREAD) #include <net/openthread.h> #endif /* * For non-invasive tracing of IRQ events. Sometimes the print logs * will shift the timings around so this trace buffer can be used to * post inspect conditions to see what sequence of events occurred. */ #define KW41_DBG_TRACE_WTRM 0 #define KW41_DBG_TRACE_RX 1 #define KW41_DBG_TRACE_TX 2 #define KW41_DBG_TRACE_CCA 3 #define KW41_DBG_TRACE_TMR3 0xFF #if defined(CONFIG_KW41_DBG_TRACE) #define KW41_DBG_TRACE_SIZE 30 struct kw41_dbg_trace { u8_t type; u32_t time; u32_t irqsts; u32_t phy_ctrl; u32_t seq_state; }; struct kw41_dbg_trace kw41_dbg[KW41_DBG_TRACE_SIZE]; int kw41_dbg_idx; #define KW_DBG_TRACE(_type, _irqsts, _phy_ctrl, _seq_state) \ do { \ kw41_dbg[kw41_dbg_idx].type = (_type); \ kw41_dbg[kw41_dbg_idx].time = \ ZLL->EVENT_TMR >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; \ kw41_dbg[kw41_dbg_idx].irqsts = (_irqsts); \ kw41_dbg[kw41_dbg_idx].phy_ctrl = (_phy_ctrl); \ kw41_dbg[kw41_dbg_idx].seq_state = (_seq_state); \ if (++kw41_dbg_idx == KW41_DBG_TRACE_SIZE) { \ kw41_dbg_idx = 0; \ } \ } while (0) #else #define KW_DBG_TRACE(_type, _irqsts, _phy_ctrl, _seq_state) #endif #define KW41Z_DEFAULT_CHANNEL 26 #define KW41Z_CCA_TIME 8 #define KW41Z_SHR_PHY_TIME 12 #define KW41Z_PER_BYTE_TIME 2 #define KW41Z_ACK_WAIT_TIME 54 #define KW41Z_PRE_RX_WAIT_TIME 1 #define KW40Z_POST_SEQ_WAIT_TIME 1 #define RADIO_0_IRQ_PRIO 0x0 #define KW41Z_FCS_LENGTH 2 #define KW41Z_PSDU_LENGTH 125 #define KW41Z_OUTPUT_POWER_MAX 2 #define KW41Z_OUTPUT_POWER_MIN (-19) #define IEEE802154_ACK_LENGTH 5 #define BM_ZLL_IRQSTS_TMRxMSK (ZLL_IRQSTS_TMR1MSK_MASK | \ ZLL_IRQSTS_TMR2MSK_MASK | \ ZLL_IRQSTS_TMR3MSK_MASK | \ ZLL_IRQSTS_TMR4MSK_MASK) /* * Clear channel assement types. Note that there is an extra one when * bit 26 is included for "No CCA before transmit" if we are handling * ACK frames but we will let the hardware handle that automatically. */ enum { KW41Z_CCA_ED, /* Energy detect */ KW41Z_CCA_MODE1, /* Energy above threshold */ KW41Z_CCA_MODE2, /* Carrier sense only */ KW41Z_CCA_MODE3 /* Mode 1 + Mode 2 */ }; /* * KW41Z has a sequencer that can run in any of the following states. */ enum { KW41Z_STATE_IDLE, KW41Z_STATE_RX, KW41Z_STATE_TX, KW41Z_STATE_CCA, KW41Z_STATE_TXRX, KW41Z_STATE_CCCA }; /* Lookup table for PA_PWR register */ static const u8_t pa_pwr_lt[22] = { 2, 2, 2, 2, 2, 2, /* -19:-14 dBm */ 4, 4, 4, /* -13:-11 dBm */ 6, 6, 6, /* -10:-8 dBm */ 8, 8, /* -7:-6 dBm */ 10, 10, /* -5:-4 dBm */ 12, /* -3 dBm */ 14, 14, /* -2:-1 dBm */ 18, 18, /* 0:1 dBm */ 24 /* 2 dBm */ }; struct kw41z_context { struct net_if *iface; u8_t mac_addr[8]; struct k_sem seq_sync; atomic_t seq_retval; u32_t rx_warmup_time; u32_t tx_warmup_time; }; static struct kw41z_context kw41z_context_data; static inline u8_t kw41z_get_instant_state(void) { return (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) >> ZLL_SEQ_STATE_SEQ_STATE_SHIFT; } static inline u8_t kw41z_get_seq_state(void) { return (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT; } static inline void kw41z_set_seq_state(u8_t state) { #if CONFIG_SOC_MKW40Z4 /* * KW40Z seems to require a small delay when switching to IDLE state * after a programmed sequence is complete. */ if (state == KW41Z_STATE_IDLE) { k_busy_wait(KW40Z_POST_SEQ_WAIT_TIME); } #endif ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_XCVSEQ_MASK) | ZLL_PHY_CTRL_XCVSEQ(state); } static inline void kw41z_wait_for_idle(void) { u8_t state = kw41z_get_instant_state(); while (state != KW41Z_STATE_IDLE) { state = kw41z_get_instant_state(); } if (state != KW41Z_STATE_IDLE) { LOG_ERR("Error waiting for idle state"); } } static void kw41z_phy_abort(void) { int key; key = irq_lock(); /* Mask SEQ interrupt */ ZLL->PHY_CTRL |= ZLL_PHY_CTRL_SEQMSK_MASK; /* Disable timer trigger (for scheduled XCVSEQ) */ if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_TMRTRIGEN_MASK) { ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMRTRIGEN_MASK; /* give the FSM enough time to start if it was triggered */ while ((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) { } } /* If XCVR is not idle, abort current SEQ */ if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_XCVSEQ_MASK) { ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_XCVSEQ_MASK; /* wait for Sequence Idle (if not already) */ while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) { } } /* Stop timers */ ZLL->PHY_CTRL &= ~(ZLL_PHY_CTRL_TMR1CMP_EN_MASK | ZLL_PHY_CTRL_TMR2CMP_EN_MASK | ZLL_PHY_CTRL_TMR3CMP_EN_MASK | ZLL_PHY_CTRL_TC3TMOUT_MASK); /* * Clear all IRQ bits to avoid unexpected interrupts. * * For Coverity, this is a pointer to a register bank and the IRQSTS * register bits get cleared when a 1 is written to them so doing a * reg=reg may generate a warning but it is needed to clear the bits. */ ZLL->IRQSTS = ZLL->IRQSTS; irq_unlock(key); } static void kw41z_isr_timeout_cleanup(void) { u32_t irqsts; /* * Set the PHY sequencer back to IDLE and disable TMR3 comparator * and timeout */ ZLL->PHY_CTRL &= ~(ZLL_PHY_CTRL_TMR3CMP_EN_MASK | ZLL_PHY_CTRL_TC3TMOUT_MASK | ZLL_PHY_CTRL_XCVSEQ_MASK); /* Mask SEQ, RX, TX and CCA interrupts */ ZLL->PHY_CTRL |= ZLL_PHY_CTRL_CCAMSK_MASK | ZLL_PHY_CTRL_RXMSK_MASK | ZLL_PHY_CTRL_TXMSK_MASK | ZLL_PHY_CTRL_SEQMSK_MASK; while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) { } irqsts = ZLL->IRQSTS; /* Mask TMR3 interrupt */ irqsts |= ZLL_IRQSTS_TMR3MSK_MASK; ZLL->IRQSTS = irqsts; } static void kw41z_isr_seq_cleanup(void) { u32_t irqsts; /* Set the PHY sequencer back to IDLE */ ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_XCVSEQ_MASK; /* Mask SEQ, RX, TX and CCA interrupts */ ZLL->PHY_CTRL |= ZLL_PHY_CTRL_CCAMSK_MASK | ZLL_PHY_CTRL_RXMSK_MASK | ZLL_PHY_CTRL_TXMSK_MASK | ZLL_PHY_CTRL_SEQMSK_MASK; while (ZLL->SEQ_STATE & ZLL_SEQ_STATE_SEQ_STATE_MASK) { } irqsts = ZLL->IRQSTS; /* Mask TMR3 interrupt */ irqsts |= ZLL_IRQSTS_TMR3MSK_MASK; /* Clear transceiver interrupts except TMRxIRQ */ irqsts &= ~(ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK); ZLL->IRQSTS = irqsts; } static inline void kw41z_enable_seq_irq(void) { ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_SEQMSK_MASK; } static inline void kw41z_disable_seq_irq(void) { ZLL->PHY_CTRL |= ZLL_PHY_CTRL_SEQMSK_MASK; } /* * Set the T3CMP timer comparator. The 'timeout' value is an offset from * now. */ static void kw41z_tmr3_set_timeout(u32_t timeout) { u32_t irqsts; /* Add in the current time so that we can get the comparator to * match appropriately to our offset time. */ timeout += ZLL->EVENT_TMR >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; /* disable TMR3 compare */ ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMR3CMP_EN_MASK; ZLL->T3CMP = timeout & ZLL_T3CMP_T3CMP_MASK; /* aknowledge TMR3 IRQ */ irqsts = ZLL->IRQSTS & BM_ZLL_IRQSTS_TMRxMSK; irqsts |= ZLL_IRQSTS_TMR3IRQ_MASK; ZLL->IRQSTS = irqsts; /* enable TMR3 compare and autosequence stop by TC3 match */ ZLL->PHY_CTRL |= (ZLL_PHY_CTRL_TMR3CMP_EN_MASK | ZLL_PHY_CTRL_TC3TMOUT_MASK); } static void kw41z_tmr3_disable(void) { u32_t irqsts; /* * disable TMR3 compare and disable autosequence stop by TC3 * match */ ZLL->PHY_CTRL &= ~(ZLL_PHY_CTRL_TMR3CMP_EN_MASK | ZLL_PHY_CTRL_TC3TMOUT_MASK); /* mask TMR3 interrupt (do not change other IRQ status) */ irqsts = ZLL->IRQSTS & BM_ZLL_IRQSTS_TMRxMSK; irqsts |= ZLL_IRQSTS_TMR3MSK_MASK; /* aknowledge TMR3 IRQ */ irqsts |= ZLL_IRQSTS_TMR3IRQ_MASK; ZLL->IRQSTS = irqsts; } static enum ieee802154_hw_caps kw41z_get_capabilities(struct device *dev) { return IEEE802154_HW_FCS | IEEE802154_HW_2_4_GHZ | IEEE802154_HW_FILTER | IEEE802154_HW_TX_RX_ACK; } static int kw41z_cca(struct device *dev) { struct kw41z_context *kw41z = dev->driver_data; kw41z_phy_abort(); k_sem_init(&kw41z->seq_sync, 0, 1); kw41z_enable_seq_irq(); ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) | ZLL_PHY_CTRL_CCATYPE(KW41Z_CCA_MODE1); kw41z_set_seq_state(KW41Z_STATE_CCA); k_sem_take(&kw41z->seq_sync, K_FOREVER); return kw41z->seq_retval; } static int kw41z_set_channel(struct device *dev, u16_t channel) { if (channel < 11 || channel > 26) { return -EINVAL; } ZLL->CHANNEL_NUM0 = channel; return 0; } static int kw41z_set_pan_id(struct device *dev, u16_t pan_id) { ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACPANID0_MASK) | ZLL_MACSHORTADDRS0_MACPANID0(pan_id); return 0; } static int kw41z_set_short_addr(struct device *dev, u16_t short_addr) { ZLL->MACSHORTADDRS0 = (ZLL->MACSHORTADDRS0 & ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) | ZLL_MACSHORTADDRS0_MACSHORTADDRS0(short_addr); return 0; } static int kw41z_set_ieee_addr(struct device *dev, const u8_t *ieee_addr) { u32_t val; memcpy(&val, ieee_addr, sizeof(val)); ZLL->MACLONGADDRS0_LSB = val; memcpy(&val, ieee_addr + sizeof(val), sizeof(val)); ZLL->MACLONGADDRS0_MSB = val; return 0; } static int kw41z_filter(struct device *dev, bool set, enum ieee802154_filter_type type, const struct ieee802154_filter *filter) { LOG_DBG("Applying filter %u", type); if (!set) { return -ENOTSUP; } if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) { return kw41z_set_ieee_addr(dev, filter->ieee_addr); } else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) { return kw41z_set_short_addr(dev, filter->short_addr); } else if (type == IEEE802154_FILTER_TYPE_PAN_ID) { return kw41z_set_pan_id(dev, filter->pan_id); } return -ENOTSUP; } static int kw41z_set_txpower(struct device *dev, s16_t dbm) { if (dbm < KW41Z_OUTPUT_POWER_MIN) { ZLL->PA_PWR = 0; } else if (dbm > KW41Z_OUTPUT_POWER_MAX) { ZLL->PA_PWR = 30; } else { ZLL->PA_PWR = pa_pwr_lt[dbm - KW41Z_OUTPUT_POWER_MIN]; } return 0; } static int kw41z_start(struct device *dev) { irq_enable(Radio_1_IRQn); kw41z_set_seq_state(KW41Z_STATE_RX); kw41z_enable_seq_irq(); return 0; } static int kw41z_stop(struct device *dev) { irq_disable(Radio_1_IRQn); kw41z_disable_seq_irq(); kw41z_set_seq_state(KW41Z_STATE_IDLE); return 0; } static u8_t kw41z_convert_lqi(u8_t hw_lqi) { if (hw_lqi >= 220U) { return 255; } else { return (hw_lqi * 51U) / 44; } } static inline void kw41z_rx(struct kw41z_context *kw41z, u8_t len) { struct net_pkt *pkt = NULL; struct net_buf *buf = NULL; u8_t pkt_len, hw_lqi; int rslt; LOG_DBG("ENTRY: len: %d", len); #if defined(CONFIG_NET_L2_OPENTHREAD) /* * OpenThread stack expects a receive frame to include the FCS */ pkt_len = len; #else pkt_len = len - KW41Z_FCS_LENGTH; #endif pkt = net_pkt_alloc_with_buffer(kw41z->iface, pkt_len, AF_UNSPEC, 0, K_NO_WAIT); if (!pkt) { LOG_ERR("No buf available"); goto out; } buf = pkt->buffer; #if CONFIG_SOC_MKW41Z4 /* PKT_BUFFER_RX needs to be accessed aligned to 16 bits */ for (u16_t reg_val = 0, i = 0; i < pkt_len; i++) { if (i % 2 == 0U) { reg_val = ZLL->PKT_BUFFER_RX[i/2U]; buf->data[i] = reg_val & 0xFF; } else { buf->data[i] = reg_val >> 8; } } #else /* CONFIG_SOC_MKW40Z4 */ /* PKT_BUFFER needs to be accessed aligned to 32 bits */ for (u32_t reg_val = 0, i = 0; i < pkt_len; i++) { switch (i % 4) { case 0: reg_val = ZLL->PKT_BUFFER[i/4U]; buf->data[i] = reg_val & 0xFF; break; case 1: buf->data[i] = (reg_val >> 8) & 0xFF; break; case 2: buf->data[i] = (reg_val >> 16) & 0xFF; break; default: buf->data[i] = reg_val >> 24; } } #endif net_buf_add(buf, pkt_len); hw_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >> ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT; net_pkt_set_ieee802154_lqi(pkt, kw41z_convert_lqi(hw_lqi)); /* ToDo: get the rssi as well and use net_pkt_set_ieee802154_rssi() */ rslt = net_recv_data(kw41z->iface, pkt); if (rslt < 0) { LOG_ERR("RCV Packet dropped by NET stack: %d", rslt); goto out; } return; out: if (pkt) { net_pkt_unref(pkt); } } static int kw41z_tx(struct device *dev, struct net_pkt *pkt, struct net_buf *frag) { struct kw41z_context *kw41z = dev->driver_data; u8_t payload_len = frag->len; u32_t tx_timeout; u8_t xcvseq; int key; /* * The transmit requests are preceded by the CCA request. On * completion of the CCA the sequencer should be in the IDLE * state. */ if (kw41z_get_seq_state() != KW41Z_STATE_IDLE) { LOG_WRN("Can't initiate new SEQ state"); return -EBUSY; } if (payload_len > KW41Z_PSDU_LENGTH) { LOG_ERR("Payload too long"); return 0; } key = irq_lock(); /* Disable the 802.15.4 radio IRQ */ ZLL->PHY_CTRL |= ZLL_PHY_CTRL_TRCV_MSK_MASK; kw41z_disable_seq_irq(); #if CONFIG_SOC_MKW41Z4 ((u8_t *)ZLL->PKT_BUFFER_TX)[0] = payload_len + KW41Z_FCS_LENGTH; memcpy(((u8_t *)ZLL->PKT_BUFFER_TX) + 1, (void *)frag->data, payload_len); #else /* CONFIG_SOC_MKW40Z4 */ ((u8_t *)ZLL->PKT_BUFFER)[0] = payload_len + KW41Z_FCS_LENGTH; memcpy(((u8_t *)ZLL->PKT_BUFFER) + 1, (void *)frag->data, payload_len); #endif /* Set CCA mode */ ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_CCATYPE_MASK) | ZLL_PHY_CTRL_CCATYPE(KW41Z_CCA_MODE1); /* Clear all IRQ flags */ ZLL->IRQSTS = ZLL->IRQSTS; /* * Current Zephyr 802.15.4 stack doesn't support ACK offload */ /* Perform automatic reception of ACK frame, if required */ if (ieee802154_is_ar_flag_set(frag)) { tx_timeout = kw41z->tx_warmup_time + KW41Z_SHR_PHY_TIME + payload_len * KW41Z_PER_BYTE_TIME + 10 + KW41Z_ACK_WAIT_TIME; LOG_DBG("AUTOACK ENABLED: len: %d, timeout: %d, seq: %d", payload_len, tx_timeout, frag->data[2]); kw41z_tmr3_set_timeout(tx_timeout); ZLL->PHY_CTRL |= ZLL_PHY_CTRL_RXACKRQD_MASK; xcvseq = KW41Z_STATE_TXRX; } else { LOG_DBG("AUTOACK DISABLED: len: %d, seq: %d", payload_len, frag->data[2]); ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_RXACKRQD_MASK; xcvseq = KW41Z_STATE_TX; } kw41z_enable_seq_irq(); /* * PHY_CTRL is sensitive to multiple writes that can kick off * the sequencer engine causing TX with AR request to send the * TX frame multiple times. * * To minimize, ensure there is only one write to PHY_CTRL with * TXRX sequence enable and the 802.15.4 radio IRQ. */ ZLL->PHY_CTRL = (ZLL->PHY_CTRL & ~ZLL_PHY_CTRL_TRCV_MSK_MASK) | xcvseq; irq_unlock(key); k_sem_take(&kw41z->seq_sync, K_FOREVER); LOG_DBG("seq_retval: %d", kw41z->seq_retval); return kw41z->seq_retval; } static void kw41z_isr(int unused) { u32_t irqsts = ZLL->IRQSTS; u8_t state = kw41z_get_seq_state(); u8_t restart_rx = 1U; u32_t rx_len; /* * Variable is used in debug output to capture the state of the * sequencer at interrupt. */ u32_t seq_state = ZLL->SEQ_STATE; LOG_DBG("ENTRY: irqsts: 0x%08X, PHY_CTRL: 0x%08X, " "SEQ_STATE: 0x%08X, SEQ_CTRL: 0x%08X, TMR: %d, state: %d", irqsts, (unsigned int)ZLL->PHY_CTRL, (unsigned int)seq_state, (unsigned int)ZLL->SEQ_CTRL_STS, (unsigned int)(ZLL->EVENT_TMR >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT), state); /* Clear interrupts */ ZLL->IRQSTS = irqsts; if (irqsts & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) { LOG_DBG("Incoming RX failed packet filtering rules: " "CODE: 0x%08X, irqsts: 0x%08X, PHY_CTRL: 0x%08X, " "SEQ_STATE: 0x%08X, state: %d", (unsigned int)ZLL->FILTERFAIL_CODE, irqsts, (unsigned int)ZLL->PHY_CTRL, (unsigned int)seq_state, state); restart_rx = 0U; } else if ((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) && (irqsts & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) { /* * There is a bug in the KW41Z where in noisy environments * the RX sequence can get lost. The watermark mask IRQ can * start TMR3 to complete the rest of the read or to assert * IRQ if the sequencer gets lost so we can reset things. * Note that a TX from the upper layers will also reset * things so the problem is contained a bit in normal * operation. */ rx_len = (irqsts & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; KW_DBG_TRACE(KW41_DBG_TRACE_WTRM, irqsts, (unsigned int)ZLL->PHY_CTRL, seq_state); if (rx_len > IEEE802154_ACK_LENGTH) { LOG_DBG("WMRK irq: seq_state: 0x%08x, rx_len: %d", seq_state, rx_len); /* * Assume the RX includes an auto-ACK so set the * timer to include the RX frame size, crc, IFS, * and ACK length and convert to symbols. * * IFS is 12 symbols * * ACK frame is 11 bytes: 4 preamble, 1 start of * frame, 1 frame length, 2 frame control, * 1 sequence, 2 FCS. Times two to convert to symbols. */ rx_len = rx_len * 2U + 12 + 22 + 2; kw41z_tmr3_set_timeout(rx_len); } restart_rx = 0U; } /* Sequence done IRQ */ if ((state != KW41Z_STATE_IDLE) && (irqsts & ZLL_IRQSTS_SEQIRQ_MASK)) { /* * PLL unlock, the autosequence has been aborted due to * PLL unlock */ if (irqsts & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK) { LOG_ERR("PLL unlock error"); kw41z_isr_seq_cleanup(); restart_rx = 1U; } /* * TMR3 timeout, the autosequence has been aborted due to * TMR3 timeout */ else if ((irqsts & ZLL_IRQSTS_TMR3IRQ_MASK) && (!(irqsts & ZLL_IRQSTS_RXIRQ_MASK)) && (state != KW41Z_STATE_TX)) { LOG_DBG("a) TMR3 timeout: irqsts: 0x%08X, " "seq_state: 0x%08X, PHY_CTRL: 0x%08X, " "state: %d", irqsts, seq_state, (unsigned int)ZLL->PHY_CTRL, state); KW_DBG_TRACE(KW41_DBG_TRACE_TMR3, irqsts, (unsigned int)ZLL->PHY_CTRL, seq_state); kw41z_isr_timeout_cleanup(); restart_rx = 1U; if (state == KW41Z_STATE_TXRX) { /* TODO: What is the right error for no ACK? */ atomic_set(&kw41z_context_data.seq_retval, -EBUSY); k_sem_give(&kw41z_context_data.seq_sync); } } else { kw41z_isr_seq_cleanup(); switch (state) { case KW41Z_STATE_RX: LOG_DBG("RX seq done: SEQ_STATE: 0x%08X", (unsigned int)seq_state); KW_DBG_TRACE(KW41_DBG_TRACE_RX, irqsts, (unsigned int)ZLL->PHY_CTRL, seq_state); kw41z_tmr3_disable(); rx_len = (ZLL->IRQSTS & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT; if (irqsts & ZLL_IRQSTS_RXIRQ_MASK) { if (rx_len != 0U) { kw41z_rx(&kw41z_context_data, rx_len); } } restart_rx = 1U; break; case KW41Z_STATE_TXRX: LOG_DBG("TXRX seq done"); kw41z_tmr3_disable(); case KW41Z_STATE_TX: LOG_DBG("TX seq done"); KW_DBG_TRACE(KW41_DBG_TRACE_TX, irqsts, (unsigned int)ZLL->PHY_CTRL, seq_state); if (irqsts & ZLL_IRQSTS_CCA_MASK) { atomic_set( &kw41z_context_data.seq_retval, -EBUSY); } else { atomic_set( &kw41z_context_data.seq_retval, 0); } k_sem_give(&kw41z_context_data.seq_sync); restart_rx = 1U; break; case KW41Z_STATE_CCA: LOG_DBG("CCA seq done"); KW_DBG_TRACE(KW41_DBG_TRACE_CCA, irqsts, (unsigned int)ZLL->PHY_CTRL, seq_state); if (irqsts & ZLL_IRQSTS_CCA_MASK) { atomic_set( &kw41z_context_data.seq_retval, -EBUSY); restart_rx = 1U; } else { atomic_set( &kw41z_context_data.seq_retval, 0); restart_rx = 0U; } k_sem_give(&kw41z_context_data.seq_sync); break; default: LOG_DBG("Unhandled state: %d", state); restart_rx = 1U; break; } } } else { /* Timer 3 Compare Match */ if ((irqsts & ZLL_IRQSTS_TMR3IRQ_MASK) && (!(irqsts & ZLL_IRQSTS_TMR3MSK_MASK))) { LOG_DBG("b) TMR3 timeout: irqsts: 0x%08X, " "seq_state: 0x%08X, state: %d", irqsts, seq_state, state); kw41z_tmr3_disable(); restart_rx = 0U; if (state != KW41Z_STATE_IDLE) { kw41z_isr_timeout_cleanup(); restart_rx = 1U; /* If we are not running an automated * sequence then handle event. TMR3 can expire * during Recv/Ack sequence where the transmit * of the ACK is not being interrupted. */ } } } /* Restart RX */ if (restart_rx) { LOG_DBG("RESET RX"); kw41z_phy_abort(); kw41z_set_seq_state(KW41Z_STATE_RX); kw41z_enable_seq_irq(); } } static inline u8_t *get_mac(struct device *dev) { struct kw41z_context *kw41z = dev->driver_data; /* * The KW40Z has two 32-bit registers for the MAC address where * 40 bits of the registers are factory programmed to be unique * and the rest are to be assigned as the "company-specific" value. * 802.15.4 defines a EUI-64 64-bit address with company specific * being 24 or 36 bits with the unique value being 24 or 40 bits. * * TODO: Grab from RSIM->MAC_LSB/MAC_MSB for the unique 40 bits * and how to allow for a OUI portion? */ u32_t *ptr = (u32_t *)(kw41z->mac_addr); UNALIGNED_PUT(sys_rand32_get(), ptr); ptr = (u32_t *)(kw41z->mac_addr + 4); UNALIGNED_PUT(sys_rand32_get(), ptr); /* * Clear bit 0 to ensure it isn't a multicast address and set * bit 1 to indicate address is locally administrered and may * not be globally unique. */ kw41z->mac_addr[0] = (kw41z->mac_addr[0] & ~0x01) | 0x02; return kw41z->mac_addr; } static int kw41z_init(struct device *dev) { struct kw41z_context *kw41z = dev->driver_data; xcvrStatus_t xcvrStatus; xcvrStatus = XCVR_Init(ZIGBEE_MODE, DR_500KBPS); if (xcvrStatus != gXcvrSuccess_c) { return -EIO; } /* Disable all timers, enable AUTOACK, mask all interrupts */ ZLL->PHY_CTRL = ZLL_PHY_CTRL_CCATYPE(KW41Z_CCA_MODE1) | ZLL_PHY_CTRL_CRC_MSK_MASK | ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK | /*ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |*/ ZLL_PHY_CTRL_RX_WMRK_MSK_MASK | ZLL_PHY_CTRL_CCAMSK_MASK | ZLL_PHY_CTRL_RXMSK_MASK | ZLL_PHY_CTRL_TXMSK_MASK | ZLL_PHY_CTRL_CCABFRTX_MASK | ZLL_PHY_CTRL_SEQMSK_MASK; #if CONFIG_SOC_MKW41Z4 ZLL->PHY_CTRL |= ZLL_IRQSTS_WAKE_IRQ_MASK; #endif ZLL->PHY_CTRL |= ZLL_PHY_CTRL_AUTOACK_MASK; /* * Clear all PP IRQ bits to avoid unexpected interrupts immediately * after init disable all timer interrupts */ ZLL->IRQSTS = ZLL->IRQSTS; /* Clear HW indirect queue */ ZLL->SAM_TABLE |= ZLL_SAM_TABLE_INVALIDATE_ALL_MASK; /* Accept FrameVersion 0 and 1 packets, reject all others */ ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_PROMISCUOUS_MASK; ZLL->RX_FRAME_FILTER &= ~ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK; ZLL->RX_FRAME_FILTER = ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3) | ZLL_RX_FRAME_FILTER_CMD_FT_MASK | ZLL_RX_FRAME_FILTER_DATA_FT_MASK | ZLL_RX_FRAME_FILTER_ACK_FT_MASK | ZLL_RX_FRAME_FILTER_BEACON_FT_MASK; /* Set prescaller to obtain 1 symbol (16us) timebase */ ZLL->TMR_PRESCALE = 0x05; kw41z_tmr3_disable(); /* Compute warmup times (scaled to 16us) */ kw41z->rx_warmup_time = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; kw41z->tx_warmup_time = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; if (kw41z->rx_warmup_time & 0x0F) { kw41z->rx_warmup_time = 1 + (kw41z->rx_warmup_time >> 4); } else { kw41z->rx_warmup_time = kw41z->rx_warmup_time >> 4; } if (kw41z->tx_warmup_time & 0x0F) { kw41z->tx_warmup_time = 1 + (kw41z->tx_warmup_time >> 4); } else { kw41z->tx_warmup_time = kw41z->tx_warmup_time >> 4; } /* Set CCA threshold to -75 dBm */ ZLL->CCA_LQI_CTRL &= ~ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK; ZLL->CCA_LQI_CTRL |= ZLL_CCA_LQI_CTRL_CCA1_THRESH(0xB5); /* Set the default power level */ kw41z_set_txpower(dev, 0); /* Adjust ACK delay to fulfill the 802.15.4 turnaround requirements */ ZLL->ACKDELAY &= ~ZLL_ACKDELAY_ACKDELAY_MASK; ZLL->ACKDELAY |= ZLL_ACKDELAY_ACKDELAY(-8); /* Adjust LQI compensation */ ZLL->CCA_LQI_CTRL &= ~ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK; ZLL->CCA_LQI_CTRL |= ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(96); /* Enable the RxWatermark IRQ */ ZLL->PHY_CTRL &= ~(ZLL_PHY_CTRL_RX_WMRK_MSK_MASK); /* Set Rx watermark level */ ZLL->RX_WTR_MARK = 0; /* Set default channel to 2405 MHZ */ kw41z_set_channel(dev, KW41Z_DEFAULT_CHANNEL); /* Unmask Transceiver Global Interrupts */ ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TRCV_MSK_MASK; /* Configure Radio IRQ */ NVIC_ClearPendingIRQ(Radio_1_IRQn); IRQ_CONNECT(Radio_1_IRQn, RADIO_0_IRQ_PRIO, kw41z_isr, 0, 0); return 0; } static void kw41z_iface_init(struct net_if *iface) { struct device *dev = net_if_get_device(iface); struct kw41z_context *kw41z = dev->driver_data; u8_t *mac = get_mac(dev); #if defined(CONFIG_KW41_DBG_TRACE) kw41_dbg_idx = 0; #endif net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154); kw41z->iface = iface; ieee802154_init(iface); } static struct ieee802154_radio_api kw41z_radio_api = { .iface_api.init = kw41z_iface_init, .get_capabilities = kw41z_get_capabilities, .cca = kw41z_cca, .set_channel = kw41z_set_channel, .filter = kw41z_filter, .set_txpower = kw41z_set_txpower, .start = kw41z_start, .stop = kw41z_stop, .tx = kw41z_tx, }; #if defined(CONFIG_NET_L2_IEEE802154) #define L2 IEEE802154_L2 #define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(IEEE802154_L2) #define MTU KW41Z_PSDU_LENGTH #elif defined(CONFIG_NET_L2_OPENTHREAD) #define L2 OPENTHREAD_L2 #define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(OPENTHREAD_L2) #define MTU 1280 #endif NET_DEVICE_INIT( kw41z, /* Device Name */ CONFIG_IEEE802154_KW41Z_DRV_NAME, /* Driver Name */ kw41z_init, /* Initialization Function */ &kw41z_context_data, /* Context data */ NULL, /* Configuration info */ CONFIG_IEEE802154_KW41Z_INIT_PRIO, /* Initial priority */ &kw41z_radio_api, /* API interface functions */ L2, /* L2 */ L2_CTX_TYPE, /* L2 context type */ MTU); /* MTU size */ |