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Defined in 3 files as a prototype:
- include/arch/arc/v2/irq.h, line 28 (as a prototype)
- include/arch/arm/cortex_m/exc.h, line 43 (as a prototype)
- include/arch/arm/cortex_m/irq.h, line 26 (as a prototype)
Defined in 2 files as a macro:
Referenced in 51 files:
- arch/arc/core/atomic.S
- arch/arc/core/cpu_idle.S
- arch/arc/core/fast_irq.S
- arch/arc/core/fault_s.S
- arch/arc/core/isr_wrapper.S
- arch/arc/core/regular_irq.S
- arch/arc/core/reset.S
- arch/arc/core/swap.S, line 24
- arch/arc/core/thread_entry_wrapper.S, line 17
- arch/arc/core/userspace.S
- arch/arc/include/vector_table.h
- arch/arm/core/cortex_m/nmi_on_reset.S, line 23
- arch/arm/core/cortex_m/reset.S
- arch/arm/core/cortex_m/vector_table.h
- arch/arm/core/cpu_idle.S
- arch/arm/core/exc_exit.S
- arch/arm/core/fault_s.S
- arch/arm/core/irq_relay.S, line 52
- arch/arm/core/isr_wrapper.S
- arch/arm/core/swap_helper.S
- arch/arm/core/userspace.S
- arch/nios2/core/crt0.S
- arch/nios2/core/exception.S
- arch/nios2/core/reset.S, line 11
- arch/nios2/core/swap.S
- arch/riscv32/core/isr.S
- arch/riscv32/core/reset.S
- arch/riscv32/core/swap.S
- arch/x86/core/cache_s.S
- arch/x86/core/crt0.S
- arch/x86/core/excstub.S
- arch/x86/core/intstub.S
- arch/x86/core/swap.S
- arch/x86/core/userspace.S
- drivers/interrupt_controller/loapic_spurious.S, line 15
- ext/hal/nxp/mcux/devices/LPC54114/gcc/startup_LPC54114_cm4.S, line 68
- include/arch/arc/v2/irq.h
- include/arch/arm/cortex_m/irq.h
- include/arch/x86/asm.h
- include/toolchain/gcc.h, line 227
- soc/arc/quark_se_c1000_ss/soc_power.S
- soc/arm/nxp_kinetis/k6x/wdog.S, line 20
- soc/arm/nxp_kinetis/kwx/wdog.S, line 20
- soc/arm/ti_lm3s6965/reboot.S
- soc/riscv32/openisa_rv32m1/soc_irq.S
- soc/riscv32/openisa_rv32m1/vector.S
- soc/riscv32/openisa_rv32m1/wdog.S, line 12
- soc/riscv32/riscv-privilege/common/soc_irq.S, line 18
- soc/riscv32/riscv-privilege/common/vector.S
- soc/x86/intel_quark/quark_se/soc_power.S
- tests/kernel/static_idt/src/test_stubs.S