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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 | /* * Copyright (c) 2018 Alexander Wachter * * SPDX-License-Identifier: Apache-2.0 */ #include <clock_control/stm32_clock_control.h> #include <clock_control.h> #include <misc/util.h> #include <string.h> #include <kernel.h> #include <soc.h> #include <errno.h> #include <stdbool.h> #include <can.h> #include "stm32_can.h" #define LOG_LEVEL CONFIG_CAN_LOG_LEVEL #include <logging/log.h> LOG_MODULE_REGISTER(stm32_can); /* * Translation tables * filter_in_bank[enum can_filter_type] = number of filters in bank for this type * reg_demand[enum can_filter_type] = how many registers are used for this type */ static const u8_t filter_in_bank[] = {2, 4, 1, 2}; static const u8_t reg_demand[] = {2, 1, 4, 2}; static void can_stm32_signal_tx_complete(struct can_mailbox *mb) { if (mb->tx_callback) { mb->tx_callback(mb->error_flags); } else { k_sem_give(&mb->tx_int_sem); } } static void can_stm32_get_msg_fifo(CAN_FIFOMailBox_TypeDef *mbox, struct zcan_frame *msg) { if (mbox->RIR & CAN_RI0R_IDE) { msg->ext_id = mbox->RIR >> CAN_RI0R_EXID_Pos; msg->id_type = CAN_EXTENDED_IDENTIFIER; } else { msg->std_id = mbox->RIR >> CAN_RI0R_STID_Pos; msg->id_type = CAN_STANDARD_IDENTIFIER; } msg->rtr = mbox->RIR & CAN_RI0R_RTR ? CAN_REMOTEREQUEST : CAN_DATAFRAME; msg->dlc = mbox->RDTR & (CAN_RDT0R_DLC >> CAN_RDT0R_DLC_Pos); msg->data_32[0] = mbox->RDLR; msg->data_32[1] = mbox->RDHR; } static inline void can_stm32_rx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data) { CAN_FIFOMailBox_TypeDef *mbox; int filter_match_index; struct zcan_frame msg; while (can->RF0R & CAN_RF0R_FMP0) { mbox = &can->sFIFOMailBox[0]; filter_match_index = ((mbox->RDTR & CAN_RDT0R_FMI) >> CAN_RDT0R_FMI_Pos); if (filter_match_index >= CONFIG_CAN_MAX_FILTER) { break; } LOG_DBG("Message on filter index %d", filter_match_index); can_stm32_get_msg_fifo(mbox, &msg); if (data->rx_response[filter_match_index]) { if (data->response_type & (1ULL << filter_match_index)) { struct k_msgq *msg_q = data->rx_response[filter_match_index]; k_msgq_put(msg_q, &msg, K_NO_WAIT); } else { can_rx_callback_t callback = data->rx_response[filter_match_index]; callback(&msg); } } /* Release message */ can->RF0R |= CAN_RF0R_RFOM0; } } static inline void can_stm32_tx_isr_handler(CAN_TypeDef *can, struct can_stm32_data *data) { u32_t bus_off; bus_off = can->ESR & CAN_ESR_BOFF; if ((can->TSR & CAN_TSR_RQCP0) | bus_off) { data->mb0.error_flags = can->TSR & CAN_TSR_TXOK0 ? CAN_TX_OK : can->TSR & CAN_TSR_TERR0 ? CAN_TX_ERR : can->TSR & CAN_TSR_ALST0 ? CAN_TX_ARB_LOST : bus_off ? CAN_TX_BUS_OFF : CAN_TX_UNKNOWN; /* clear the request. */ can->TSR |= CAN_TSR_RQCP0; can_stm32_signal_tx_complete(&data->mb0); } if ((can->TSR & CAN_TSR_RQCP1) | bus_off) { data->mb1.error_flags = can->TSR & CAN_TSR_TXOK1 ? CAN_TX_OK : can->TSR & CAN_TSR_TERR1 ? CAN_TX_ERR : can->TSR & CAN_TSR_ALST1 ? CAN_TX_ARB_LOST : bus_off ? CAN_TX_BUS_OFF : CAN_TX_UNKNOWN; /* clear the request. */ can->TSR |= CAN_TSR_RQCP1; can_stm32_signal_tx_complete(&data->mb1); } if ((can->TSR & CAN_TSR_RQCP2) | bus_off) { data->mb2.error_flags = can->TSR & CAN_TSR_TXOK2 ? CAN_TX_OK : can->TSR & CAN_TSR_TERR2 ? CAN_TX_ERR : can->TSR & CAN_TSR_ALST2 ? CAN_TX_ARB_LOST : bus_off ? CAN_TX_BUS_OFF : CAN_TX_UNKNOWN; /* clear the request. */ can->TSR |= CAN_TSR_RQCP2; can_stm32_signal_tx_complete(&data->mb2); } if (can->TSR & CAN_TSR_TME) { k_sem_give(&data->tx_int_sem); } } #ifdef CONFIG_SOC_SERIES_STM32F0X static void can_stm32_isr(void *arg) { struct device *dev; struct can_stm32_data *data; const struct can_stm32_config *cfg; CAN_TypeDef *can; dev = (struct device *)arg; data = DEV_DATA(dev); cfg = DEV_CFG(dev); can = cfg->can; can_stm32_tx_isr_handler(can, data); can_stm32_rx_isr_handler(can, data); } #else static void can_stm32_rx_isr(void *arg) { struct device *dev; struct can_stm32_data *data; const struct can_stm32_config *cfg; CAN_TypeDef *can; dev = (struct device *)arg; data = DEV_DATA(dev); cfg = DEV_CFG(dev); can = cfg->can; can_stm32_rx_isr_handler(can, data); } static void can_stm32_tx_isr(void *arg) { struct device *dev; struct can_stm32_data *data; const struct can_stm32_config *cfg; CAN_TypeDef *can; dev = (struct device *)arg; data = DEV_DATA(dev); cfg = DEV_CFG(dev); can = cfg->can; can_stm32_tx_isr_handler(can, data); } #endif void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { ARG_UNUSED(hcan); } int can_stm32_runtime_configure(struct device *dev, enum can_mode mode, u32_t bitrate) { CAN_HandleTypeDef hcan; const struct can_stm32_config *cfg = DEV_CFG(dev); CAN_TypeDef *can = cfg->can; struct device *clock; u32_t clock_rate; u32_t prescaler; u32_t hal_mode; int hal_ret; u32_t bs1; u32_t bs2; u32_t sjw; int ret; clock = device_get_binding(STM32_CLOCK_CONTROL_NAME); __ASSERT_NO_MSG(clock); hcan.Instance = can; ret = clock_control_get_rate(clock, (clock_control_subsys_t *) &cfg->pclken, &clock_rate); if (ret != 0) { LOG_ERR("Failed call clock_control_get_rate: return [%d]", ret); return -EIO; } if (!bitrate) { bitrate = cfg->bus_speed; } prescaler = clock_rate / (BIT_SEG_LENGTH(cfg) * bitrate); if (prescaler == 0U || prescaler > 1024) { LOG_ERR("HAL_CAN_Init failed: prescaler > max (%d > 1024)", prescaler); return -EINVAL; } if (clock_rate % (BIT_SEG_LENGTH(cfg) * bitrate)) { LOG_ERR("Prescaler is not a natural number! " "prescaler = clock_rate / ((PROP_SEG1 + SEG2 + 1)" " * bus_speed); " "prescaler = %d / ((%d + %d + 1) * %d)", clock_rate, cfg->prop_bs1, cfg->bs2, bitrate); } __ASSERT(cfg->sjw <= 0x03, "SJW maximum is 3"); __ASSERT(cfg->prop_bs1 <= 0x0F, "PROP_BS1 maximum is 15"); __ASSERT(cfg->bs2 <= 0x07, "BS2 maximum is 7"); bs1 = ((cfg->prop_bs1 & 0x0F) - 1) << CAN_BTR_TS1_Pos; bs2 = ((cfg->bs2 & 0x07) - 1) << CAN_BTR_TS2_Pos; sjw = ((cfg->sjw & 0x07) - 1) << CAN_BTR_SJW_Pos; hal_mode = mode == CAN_NORMAL_MODE ? CAN_MODE_NORMAL : mode == CAN_LOOPBACK_MODE ? CAN_MODE_LOOPBACK : mode == CAN_SILENT_MODE ? CAN_MODE_SILENT : CAN_MODE_SILENT_LOOPBACK; hcan.Init.TTCM = DISABLE; hcan.Init.ABOM = DISABLE; hcan.Init.AWUM = DISABLE; hcan.Init.NART = DISABLE; hcan.Init.RFLM = DISABLE; hcan.Init.TXFP = DISABLE; hcan.Init.Mode = hal_mode; hcan.Init.SJW = sjw; hcan.Init.BS1 = bs1; hcan.Init.BS2 = bs2; hcan.Init.Prescaler = prescaler; hcan.State = HAL_CAN_STATE_RESET; hal_ret = HAL_CAN_Init(&hcan); if (hal_ret != HAL_OK) { LOG_ERR("HAL_CAN_Init failed: %d", hal_ret); return -EIO; } LOG_DBG("Runtime configure of %s done", dev->config->name); return 0; } static int can_stm32_init(struct device *dev) { const struct can_stm32_config *cfg = DEV_CFG(dev); struct can_stm32_data *data = DEV_DATA(dev); CAN_TypeDef *can = cfg->can; struct device *clock; int ret; k_mutex_init(&data->tx_mutex); k_mutex_init(&data->set_filter_mutex); k_sem_init(&data->tx_int_sem, 0, 1); k_sem_init(&data->mb0.tx_int_sem, 0, 1); k_sem_init(&data->mb1.tx_int_sem, 0, 1); k_sem_init(&data->mb2.tx_int_sem, 0, 1); data->mb0.tx_callback = NULL; data->mb1.tx_callback = NULL; data->mb2.tx_callback = NULL; data->filter_usage = (1ULL << CAN_MAX_NUMBER_OF_FILTERS) - 1ULL; (void)memset(data->rx_response, 0, sizeof(void *) * CONFIG_CAN_MAX_FILTER); data->response_type = 0U; clock = device_get_binding(STM32_CLOCK_CONTROL_NAME); __ASSERT_NO_MSG(clock); ret = clock_control_on(clock, (clock_control_subsys_t *) &cfg->pclken); if (ret != 0) { LOG_ERR("HAL_CAN_Init clock control on failed: %d", ret); return -EIO; } ret = can_stm32_runtime_configure(dev, CAN_NORMAL_MODE, 0); if (ret) { return ret; } cfg->config_irq(can); can->IER |= CAN_IT_TME; LOG_INF("Init of %s done", dev->config->name); return 0; } int can_stm32_send(struct device *dev, const struct zcan_frame *msg, s32_t timeout, can_tx_callback_t callback) { const struct can_stm32_config *cfg = DEV_CFG(dev); struct can_stm32_data *data = DEV_DATA(dev); CAN_TypeDef *can = cfg->can; u32_t transmit_status_register = can->TSR; CAN_TxMailBox_TypeDef *mailbox = NULL; struct k_mutex *tx_mutex = &data->tx_mutex; struct can_mailbox *mb = NULL; LOG_DBG("Sending %d bytes on %s. " "Id: 0x%x, " "ID type: %s, " "Remote Frame: %s" , msg->dlc, dev->config->name , msg->id_type == CAN_STANDARD_IDENTIFIER ? msg->std_id : msg->ext_id , msg->id_type == CAN_STANDARD_IDENTIFIER ? "standard" : "extended" , msg->rtr == CAN_DATAFRAME ? "no" : "yes"); __ASSERT(msg->dlc == 0U || msg->data != NULL, "Dataptr is null"); __ASSERT(msg->dlc <= CAN_MAX_DLC, "DLC > 8"); if (can->ESR & CAN_ESR_BOFF) { return CAN_TX_BUS_OFF; } k_mutex_lock(tx_mutex, K_FOREVER); while (!(transmit_status_register & CAN_TSR_TME)) { k_mutex_unlock(tx_mutex); LOG_DBG("Transmit buffer full. Wait with timeout (%dms)", timeout); if (k_sem_take(&data->tx_int_sem, timeout)) { return CAN_TIMEOUT; } k_mutex_lock(tx_mutex, K_FOREVER); transmit_status_register = can->TSR; } if (transmit_status_register & CAN_TSR_TME0) { LOG_DBG("Using mailbox 0"); mailbox = &can->sTxMailBox[CAN_TXMAILBOX_0]; mb = &(data->mb0); } else if (transmit_status_register & CAN_TSR_TME1) { LOG_DBG("Using mailbox 1"); mailbox = &can->sTxMailBox[CAN_TXMAILBOX_1]; mb = &data->mb1; } else if (transmit_status_register & CAN_TSR_TME2) { LOG_DBG("Using mailbox 2"); mailbox = &can->sTxMailBox[CAN_TXMAILBOX_2]; mb = &data->mb2; } mb->tx_callback = callback; k_sem_reset(&mb->tx_int_sem); /* mailbix identifier register setup */ mailbox->TIR &= CAN_TI0R_TXRQ; if (msg->id_type == CAN_STANDARD_IDENTIFIER) { mailbox->TIR |= (msg->std_id << CAN_TI0R_STID_Pos); } else { mailbox->TIR |= (msg->ext_id << CAN_TI0R_EXID_Pos) | CAN_TI0R_IDE; } if (msg->rtr == CAN_REMOTEREQUEST) { mailbox->TIR |= CAN_TI1R_RTR; } mailbox->TDTR = (mailbox->TDTR & ~CAN_TDT1R_DLC) | ((msg->dlc & 0xF) << CAN_TDT1R_DLC_Pos); mailbox->TDLR = msg->data_32[0]; mailbox->TDHR = msg->data_32[1]; mailbox->TIR |= CAN_TI0R_TXRQ; k_mutex_unlock(tx_mutex); if (callback == NULL) { k_sem_take(&mb->tx_int_sem, K_FOREVER); return mb->error_flags; } return 0; } static inline int can_stm32_check_free(void **arr, int start, int end) { int i; for (i = start; i <= end; i++) { if (arr[i] != NULL) { return 0; } } return 1; } static int can_stm32_shift_arr(void **arr, int start, int count) { void **start_ptr = arr + start; size_t cnt; if (start > CONFIG_CAN_MAX_FILTER) { return CAN_NO_FREE_FILTER; } if (count > 0) { void *move_dest; /* Check if nothing used will be overwritten */ if (!can_stm32_check_free(arr, CONFIG_CAN_MAX_FILTER - count, CONFIG_CAN_MAX_FILTER - 1)) { return CAN_NO_FREE_FILTER; } /* No need to shift. Destination is already outside the arr*/ if ((start + count) >= CONFIG_CAN_MAX_FILTER) { return 0; } cnt = (CONFIG_CAN_MAX_FILTER - start - count) * sizeof(void *); move_dest = start_ptr + count; memmove(move_dest, start_ptr, cnt); (void)memset(start_ptr, 0, count * sizeof(void *)); } else if (count < 0) { count = -count; if (start - count < 0) { return CAN_NO_FREE_FILTER; } cnt = (CONFIG_CAN_MAX_FILTER - start) * sizeof(void *); memmove(start_ptr - count, start_ptr, cnt); (void)memset(arr + CONFIG_CAN_MAX_FILTER - count, 0, count * sizeof(void *)); } return 0; } static inline void can_stm32_shift_bits(u64_t *bits, int start, int count) { u64_t mask_right; u64_t mask_left; if (count > 0) { mask_right = ~(UINT64_MAX << start); *bits = (*bits & mask_right) | ((*bits & ~mask_right) << count); } else if (count < 0) { count = -count; mask_left = UINT64_MAX << start; mask_right = ~(UINT64_MAX << (start - count)); *bits = (*bits & mask_right) | ((*bits & mask_left) >> count); } } enum can_filter_type can_stm32_get_filter_type(int bank_nr, u32_t mode_reg, u32_t scale_reg) { u32_t mode_masked = (mode_reg >> bank_nr) & 0x01; u32_t scale_masked = (scale_reg >> bank_nr) & 0x01; enum can_filter_type type = (scale_masked << 1) | mode_masked; return type; } static int can_calc_filter_index(int filter_nr, u32_t mode_reg, u32_t scale_reg) { int filter_bank = filter_nr / 4; int cnt = 0; u32_t mode_masked, scale_masked; enum can_filter_type filter_type; /*count filters in the banks before */ for (int i = 0; i < filter_bank; i++) { filter_type = can_stm32_get_filter_type(i, mode_reg, scale_reg); cnt += filter_in_bank[filter_type]; } /* plus the filters in the same bank */ mode_masked = mode_reg & (1U << filter_bank); scale_masked = scale_reg & (1U << filter_bank); cnt += (!scale_masked && mode_masked) ? filter_nr & 0x03 : (filter_nr & 0x03) >> 1; return cnt; } static void can_stm32_set_filter_bank(int filter_nr, CAN_FilterRegister_TypeDef *filter_reg, enum can_filter_type filter_type, u32_t id, u32_t mask) { switch (filter_type) { case CAN_FILTER_STANDARD: switch (filter_nr & 0x03) { case 0: filter_reg->FR1 = (filter_reg->FR1 & 0xFFFF0000) | id; break; case 1: filter_reg->FR1 = (filter_reg->FR1 & 0x0000FFFF) | (id << 16); break; case 2: filter_reg->FR2 = (filter_reg->FR2 & 0xFFFF0000) | id; break; case 3: filter_reg->FR2 = (filter_reg->FR2 & 0x0000FFFF) | (id << 16); break; } break; case CAN_FILTER_STANDARD_MASKED: switch (filter_nr & 0x02) { case 0: filter_reg->FR1 = id | (mask << 16); break; case 2: filter_reg->FR2 = id | (mask << 16); break; } break; case CAN_FILTER_EXTENDED: switch (filter_nr & 0x02) { case 0: filter_reg->FR1 = id; break; case 2: filter_reg->FR2 = id; break; } break; case CAN_FILTER_EXTENDED_MASKED: filter_reg->FR1 = id; filter_reg->FR2 = mask; break; } } static inline void can_stm32_set_mode_scale(enum can_filter_type filter_type, u32_t *mode_reg, u32_t *scale_reg, int filter_nr) { u32_t mode_reg_bit = (filter_type & 0x01) << filter_nr; u32_t scale_reg_bit = (filter_type >> 1) << filter_nr; *mode_reg &= ~(1 << filter_nr); *mode_reg |= mode_reg_bit; *scale_reg &= ~(1 << filter_nr); *scale_reg |= scale_reg_bit; } static inline u32_t can_generate_std_mask(const struct zcan_filter *filter) { return (filter->std_id_mask << CAN_FIRX_STD_ID_POS) | (filter->rtr_mask << CAN_FIRX_STD_RTR_POS) | (1U << CAN_FIRX_STD_IDE_POS); } static inline u32_t can_generate_ext_mask(const struct zcan_filter *filter) { return (filter->ext_id_mask << CAN_FIRX_EXT_EXT_ID_POS) | (filter->rtr_mask << CAN_FIRX_EXT_RTR_POS) | (1U << CAN_FIRX_EXT_IDE_POS); } static inline u32_t can_generate_std_id(const struct zcan_filter *filter) { return (filter->std_id << CAN_FIRX_STD_ID_POS) | (filter->rtr << CAN_FIRX_STD_RTR_POS); } static inline u32_t can_generate_ext_id(const struct zcan_filter *filter) { return (filter->ext_id << CAN_FIRX_EXT_EXT_ID_POS) | (filter->rtr << CAN_FIRX_EXT_RTR_POS) | (1U << CAN_FIRX_EXT_IDE_POS); } static inline int can_stm32_set_filter(const struct zcan_filter *filter, struct can_stm32_data *device_data, CAN_TypeDef *can, int *filter_index) { u32_t mask = 0U; u32_t id = 0U; int filter_nr = 0; int filter_index_new = CAN_NO_FREE_FILTER; int bank_nr; u32_t bank_bit; int register_demand; enum can_filter_type filter_type; enum can_filter_type bank_mode; if (filter->id_type == CAN_STANDARD_IDENTIFIER) { id = can_generate_std_id(filter); filter_type = CAN_FILTER_STANDARD; if (filter->std_id_mask != CAN_STD_ID_MASK) { mask = can_generate_std_mask(filter); filter_type = CAN_FILTER_STANDARD_MASKED; } } else { id = can_generate_ext_id(filter); filter_type = CAN_FILTER_EXTENDED; if (filter->ext_id_mask != CAN_EXT_ID_MASK) { mask = can_generate_ext_mask(filter); filter_type = CAN_FILTER_EXTENDED_MASKED; } } register_demand = reg_demand[filter_type]; LOG_DBG("Setting filter ID: 0x%x, mask: 0x%x", filter->ext_id, filter->ext_id_mask); LOG_DBG("Filter type: %s ID %s mask (%d)", (filter_type == CAN_FILTER_STANDARD || filter_type == CAN_FILTER_STANDARD_MASKED) ? "standard" : "extended", (filter_type == CAN_FILTER_STANDARD_MASKED || filter_type == CAN_FILTER_EXTENDED_MASKED) ? "with" : "without", filter_type); do { u64_t usage_shifted = (device_data->filter_usage >> filter_nr); u64_t usage_demand_mask = (1ULL << register_demand) - 1; bool bank_is_empty; bank_nr = filter_nr / 4; bank_bit = (1U << bank_nr); bank_mode = can_stm32_get_filter_type(bank_nr, can->FM1R, can->FS1R); bank_is_empty = CAN_BANK_IS_EMPTY(device_data->filter_usage, bank_nr); if (!bank_is_empty && bank_mode != filter_type) { filter_nr = (bank_nr + 1) * 4; } else if (usage_shifted & usage_demand_mask) { device_data->filter_usage &= ~(usage_demand_mask << filter_nr); break; } else { filter_nr += register_demand; } if (!usage_shifted) { LOG_INF("No free filter bank found"); return CAN_NO_FREE_FILTER; } } while (filter_nr < CAN_MAX_NUMBER_OF_FILTERS); /* set the filter init mode */ can->FMR |= CAN_FMR_FINIT; can->FA1R &= ~bank_bit; /* TODO fifo balancing */ if (filter_type != bank_mode) { int shift_width, start_index; int res; u32_t mode_reg = can->FM1R; u32_t scale_reg = can->FS1R; can_stm32_set_mode_scale(filter_type, &mode_reg, &scale_reg, filter_nr); shift_width = filter_in_bank[filter_type] - filter_in_bank[bank_mode]; filter_index_new = can_calc_filter_index(filter_nr, mode_reg, scale_reg); start_index = filter_index_new + filter_in_bank[bank_mode]; if (shift_width && start_index <= CAN_MAX_NUMBER_OF_FILTERS) { res = can_stm32_shift_arr(device_data->rx_response, start_index, shift_width); if (filter_index_new >= CONFIG_CAN_MAX_FILTER || res) { LOG_INF("No space for a new filter!"); filter_nr = CAN_NO_FREE_FILTER; goto done; } can_stm32_shift_bits(&device_data->response_type, start_index, shift_width); } can->FM1R = mode_reg; can->FS1R = scale_reg; } else { filter_index_new = can_calc_filter_index(filter_nr, can->FM1R, can->FS1R); if (filter_index_new >= CAN_MAX_NUMBER_OF_FILTERS) { filter_nr = CAN_NO_FREE_FILTER; goto done; } } can_stm32_set_filter_bank(filter_nr, &can->sFilterRegister[bank_nr], filter_type, id, mask); done: can->FA1R |= bank_bit; can->FMR &= ~(CAN_FMR_FINIT); LOG_DBG("Filter set! Filter number: %d (index %d)", filter_nr, filter_index_new); *filter_index = filter_index_new; return filter_nr; } static inline int can_stm32_attach(struct device *dev, void *response_ptr, const struct zcan_filter *filter, int *filter_index) { const struct can_stm32_config *cfg = DEV_CFG(dev); struct can_stm32_data *data = DEV_DATA(dev); CAN_TypeDef *can = cfg->can; int filter_index_tmp = 0; int filter_nr; filter_nr = can_stm32_set_filter(filter, data, can, &filter_index_tmp); if (filter_nr != CAN_NO_FREE_FILTER) { data->rx_response[filter_index_tmp] = response_ptr; } *filter_index = filter_index_tmp; return filter_nr; } int can_stm32_attach_msgq(struct device *dev, struct k_msgq *msgq, const struct zcan_filter *filter) { int filter_nr; int filter_index; struct can_stm32_data *data = DEV_DATA(dev); k_mutex_lock(&data->set_filter_mutex, K_FOREVER); filter_nr = can_stm32_attach(dev, msgq, filter, &filter_index); data->response_type |= (1ULL << filter_index); k_mutex_unlock(&data->set_filter_mutex); return filter_nr; } int can_stm32_attach_isr(struct device *dev, can_rx_callback_t isr, const struct zcan_filter *filter) { struct can_stm32_data *data = DEV_DATA(dev); int filter_nr; int filter_index; k_mutex_lock(&data->set_filter_mutex, K_FOREVER); filter_nr = can_stm32_attach(dev, isr, filter, &filter_index); data->response_type &= ~(1ULL << filter_index); k_mutex_unlock(&data->set_filter_mutex); return filter_nr; } void can_stm32_detach(struct device *dev, int filter_nr) { const struct can_stm32_config *cfg = DEV_CFG(dev); struct can_stm32_data *data = DEV_DATA(dev); CAN_TypeDef *can = cfg->can; int bank_nr; int filter_index; u32_t bank_bit; u32_t mode_reg; u32_t scale_reg; enum can_filter_type type; u32_t reset_mask; __ASSERT_NO_MSG(filter_nr >= 0 && filter_nr < CAN_MAX_NUMBER_OF_FILTERS); k_mutex_lock(&data->set_filter_mutex, K_FOREVER); bank_nr = filter_nr / 4; bank_bit = (1U << bank_nr); mode_reg = can->FM1R; scale_reg = can->FS1R; filter_index = can_calc_filter_index(filter_nr, mode_reg, scale_reg); type = can_stm32_get_filter_type(bank_nr, mode_reg, scale_reg); LOG_DBG("Detatch filter number %d (index %d), type %d", filter_nr, filter_index, type); reset_mask = ((1 << (reg_demand[type])) - 1) << filter_nr; data->filter_usage |= reset_mask; can->FMR |= CAN_FMR_FINIT; can->FA1R &= ~bank_bit; can_stm32_set_filter_bank(filter_nr, &can->sFilterRegister[bank_nr], type, 0, 0xFFFFFFFF); if (!CAN_BANK_IS_EMPTY(data->filter_usage, bank_nr)) { can->FA1R |= bank_bit; } else { LOG_DBG("Bank number %d is empty -> deakivate", bank_nr); } can->FMR &= ~(CAN_FMR_FINIT); data->rx_response[filter_index] = NULL; data->response_type &= ~(1ULL << filter_index); k_mutex_unlock(&data->set_filter_mutex); } static const struct can_driver_api can_api_funcs = { .configure = can_stm32_runtime_configure, .send = can_stm32_send, .attach_msgq = can_stm32_attach_msgq, .attach_isr = can_stm32_attach_isr, .detach = can_stm32_detach }; #ifdef CONFIG_CAN_1 static void config_can_1_irq(CAN_TypeDef *can); static const struct can_stm32_config can_stm32_cfg_1 = { .can = (CAN_TypeDef *)DT_CAN_1_BASE_ADDRESS, .bus_speed = DT_CAN_1_BUS_SPEED, .sjw = DT_CAN_1_SJW, .prop_bs1 = DT_CAN_1_PROP_SEG_PHASE_SEG1, .bs2 = DT_CAN_1_PHASE_SEG2, .pclken = { .enr = DT_CAN_1_CLOCK_BITS, .bus = DT_CAN_1_CLOCK_BUS, }, .config_irq = config_can_1_irq }; static struct can_stm32_data can_stm32_dev_data_1; DEVICE_AND_API_INIT(can_stm32_1, DT_CAN_1_NAME, &can_stm32_init, &can_stm32_dev_data_1, &can_stm32_cfg_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &can_api_funcs); static void config_can_1_irq(CAN_TypeDef *can) { LOG_DBG("Enable CAN1 IRQ"); #ifdef CONFIG_SOC_SERIES_STM32F0X IRQ_CONNECT(DT_CAN_1_IRQ, DT_CAN_1_IRQ_PRIORITY, can_stm32_isr, DEVICE_GET(can_stm32_1), 0); irq_enable(DT_CAN_1_IRQ); #else IRQ_CONNECT(DT_CAN_1_IRQ_RX0, DT_CAN_1_IRQ_PRIORITY, can_stm32_rx_isr, DEVICE_GET(can_stm32_1), 0); irq_enable(DT_CAN_1_IRQ_RX0); IRQ_CONNECT(DT_CAN_1_IRQ_TX, DT_CAN_1_IRQ_PRIORITY, can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); irq_enable(DT_CAN_1_IRQ_TX); IRQ_CONNECT(DT_CAN_1_IRQ_SCE, DT_CAN_1_IRQ_PRIORITY, can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); irq_enable(DT_CAN_1_IRQ_SCE); #endif can->IER |= CAN_IT_TME | CAN_IT_ERR | CAN_IT_FMP0 | CAN_IT_FMP1; } #if defined(CONFIG_NET_SOCKETS_CAN) #include "socket_can_generic.h" static int socket_can_init_1(struct device *dev) { struct device *can_dev = DEVICE_GET(can_stm32_1); struct socket_can_context *socket_context = dev->driver_data; LOG_DBG("Init socket CAN device %p (%s) for dev %p (%s)", dev, dev->config->name, can_dev, can_dev->config->name); socket_context->can_dev = can_dev; socket_context->msgq = &socket_can_msgq; socket_context->rx_tid = k_thread_create(&socket_context->rx_thread_data, rx_thread_stack, K_THREAD_STACK_SIZEOF(rx_thread_stack), rx_thread, socket_context, NULL, NULL, RX_THREAD_PRIORITY, 0, K_NO_WAIT); return 0; } NET_DEVICE_INIT(socket_can_stm32_1, SOCKET_CAN_NAME_1, socket_can_init_1, &socket_can_context_1, NULL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &socket_can_api, CANBUS_L2, NET_L2_GET_CTX_TYPE(CANBUS_L2), CAN_MTU); #endif /* CONFIG_NET_SOCKETS_CAN */ #endif /*CONFIG_CAN_1*/ |