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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 | /* * Copyright (c) 2014 Wind River Systems, Inc. * Copyright (c) 2017 Oticon A/S * * SPDX-License-Identifier: Apache-2.0 * * SW side of the IRQ handling */ #include <stdint.h> #include "irq_handler.h" #include "irq_offload.h" #include "kernel_structs.h" #include "kernel_internal.h" #include "kswap.h" #include "irq_ctrl.h" #include "posix_core.h" #include "board_soc.h" #include "sw_isr_table.h" #include "soc.h" #include <tracing.h> typedef void (*normal_irq_f_ptr)(void *); typedef int (*direct_irq_f_ptr)(void); typedef struct _isr_list isr_table_entry_t; static isr_table_entry_t irq_vector_table[N_IRQS] = { { 0 } }; static int currently_running_irq = -1; static inline void vector_to_irq(int irq_nbr, int *may_swap) { /* * As in this architecture an irq (code) executes in 0 time, * it is a bit senseless to call z_int_latency_start/stop() */ /* z_int_latency_start(); */ sys_trace_isr_enter(); if (irq_vector_table[irq_nbr].func == NULL) { /* LCOV_EXCL_BR_LINE */ /* LCOV_EXCL_START */ posix_print_error_and_exit("Received irq %i without a " "registered handler\n", irq_nbr); /* LCOV_EXCL_STOP */ } else { if (irq_vector_table[irq_nbr].flags & ISR_FLAG_DIRECT) { *may_swap |= ((direct_irq_f_ptr) irq_vector_table[irq_nbr].func)(); } else { #ifdef CONFIG_SYS_POWER_MANAGEMENT posix_irq_check_idle_exit(); #endif ((normal_irq_f_ptr)irq_vector_table[irq_nbr].func) (irq_vector_table[irq_nbr].param); *may_swap = 1; } } sys_trace_isr_exit(); /* z_int_latency_stop(); */ } /** * When an interrupt is raised, this function is called to handle it and, if * needed, swap to a re-enabled thread * * Note that even that this function is executing in a Zephyr thread, it is * effectively the model of the interrupt controller passing context to the IRQ * handler and therefore its priority handling */ void posix_irq_handler(void) { uint64_t irq_lock; int irq_nbr; static int may_swap; irq_lock = hw_irq_ctrl_get_current_lock(); if (irq_lock) { /* "spurious" wakes can happen with interrupts locked */ return; } if (_kernel.nested == 0) { may_swap = 0; } _kernel.nested++; while ((irq_nbr = hw_irq_ctrl_get_highest_prio_irq()) != -1) { int last_current_running_prio = hw_irq_ctrl_get_cur_prio(); int last_running_irq = currently_running_irq; hw_irq_ctrl_set_cur_prio(hw_irq_ctrl_get_prio(irq_nbr)); hw_irq_ctrl_clear_irq(irq_nbr); currently_running_irq = irq_nbr; vector_to_irq(irq_nbr, &may_swap); currently_running_irq = last_running_irq; hw_irq_ctrl_set_cur_prio(last_current_running_prio); } _kernel.nested--; /* Call swap if all the following is true: * 1) may_swap was enabled * 2) We are not nesting irq_handler calls (interrupts) * 3) Next thread to run in the ready queue is not this thread */ if (may_swap && (hw_irq_ctrl_get_cur_prio() == 256) && (_kernel.ready_q.cache != _current)) { (void)z_swap_irqlock(irq_lock); } } /** * Thru this function the IRQ controller can raise an immediate interrupt which * will interrupt the SW itself * (this function should only be called from the HW model code, from SW threads) */ void posix_irq_handler_im_from_sw(void) { /* * if a higher priority interrupt than the possibly currently running is * pending we go immediately into irq_handler() to vector into its * handler */ if (hw_irq_ctrl_get_highest_prio_irq() != -1) { if (!posix_is_cpu_running()) { /* LCOV_EXCL_BR_LINE */ /* LCOV_EXCL_START */ posix_print_error_and_exit("programming error: %s " "called from a HW model thread\n", __func__); /* LCOV_EXCL_STOP */ } posix_irq_handler(); } } /** * @brief Disable all interrupts on the CPU * * This routine disables interrupts. It can be called from either interrupt, * task or fiber level. This routine returns an architecture-dependent * lock-out key representing the "interrupt disable state" prior to the call; * this key can be passed to irq_unlock() to re-enable interrupts. * * The lock-out key should only be used as the argument to the irq_unlock() * API. It should never be used to manually re-enable interrupts or to inspect * or manipulate the contents of the source register. * * This function can be called recursively: it will return a key to return the * state of interrupt locking to the previous level. * * WARNINGS * Invoking a kernel routine with interrupts locked may result in * interrupts being re-enabled for an unspecified period of time. If the * called routine blocks, interrupts will be re-enabled while another * thread executes, or while the system is idle. * * The "interrupt disable state" is an attribute of a thread. Thus, if a * fiber or task disables interrupts and subsequently invokes a kernel * routine that causes the calling thread to block, the interrupt * disable state will be restored when the thread is later rescheduled * for execution. * * @return An architecture-dependent lock-out key representing the * "interrupt disable state" prior to the call. * */ unsigned int posix_irq_lock(void) { return hw_irq_ctrl_change_lock(true); } unsigned int z_arch_irq_lock(void) { return posix_irq_lock(); } /** * * @brief Enable all interrupts on the CPU * * This routine re-enables interrupts on the CPU. The @a key parameter is a * board-dependent lock-out key that is returned by a previous invocation of * board_irq_lock(). * * This routine can be called from either interrupt, task or fiber level. * * @return N/A * */ void posix_irq_unlock(unsigned int key) { hw_irq_ctrl_change_lock(key); } void z_arch_irq_unlock(unsigned int key) { posix_irq_unlock(key); } void posix_irq_full_unlock(void) { hw_irq_ctrl_change_lock(false); } void z_arch_irq_enable(unsigned int irq) { hw_irq_ctrl_enable_irq(irq); } void z_arch_irq_disable(unsigned int irq) { hw_irq_ctrl_disable_irq(irq); } int z_arch_irq_is_enabled(unsigned int irq) { return hw_irq_ctrl_is_irq_enabled(irq); } int posix_get_current_irq(void) { return currently_running_irq; } /** * Configure a static interrupt. * * _isr_declare will populate the interrupt table table with the interrupt's * parameters, the vector table and the software ISR table. * * We additionally set the priority in the interrupt controller at * runtime. * * @param irq_p IRQ line number * @param flags [plug it directly (1), or as a SW managed interrupt (0)] * @param isr_p Interrupt service routine * @param isr_param_p ISR parameter * @param flags_p IRQ options */ void _isr_declare(unsigned int irq_p, int flags, void isr_p(void *), void *isr_param_p) { irq_vector_table[irq_p].irq = irq_p; irq_vector_table[irq_p].func = isr_p; irq_vector_table[irq_p].param = isr_param_p; irq_vector_table[irq_p].flags = flags; } /* * @internal * * @brief Set an interrupt's priority * * Lower values take priority over higher values. * * @return N/A */ void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) { hw_irq_ctrl_prio_set(irq, prio); } /** * Similar to ARM's NVIC_SetPendingIRQ * set a pending IRQ from SW * * Note that this will interrupt immediately if the interrupt is not masked and * IRQs are not locked, and this interrupt has higher priority than a possibly * currently running interrupt */ void posix_sw_set_pending_IRQ(unsigned int IRQn) { hw_irq_ctrl_raise_im_from_sw(IRQn); } /** * Similar to ARM's NVIC_ClearPendingIRQ * clear a pending irq from SW */ void posix_sw_clear_pending_IRQ(unsigned int IRQn) { hw_irq_ctrl_clear_irq(IRQn); } /** * Storage for functions offloaded to IRQ */ static irq_offload_routine_t off_routine; static void *off_parameter; /** * IRQ handler for the SW interrupt assigned to irq_offload() */ static void offload_sw_irq_handler(void *a) { ARG_UNUSED(a); off_routine(off_parameter); } /** * @brief Run a function in interrupt context * * Raise the SW IRQ assigned to handled this */ void irq_offload(irq_offload_routine_t routine, void *parameter) { off_routine = routine; off_parameter = parameter; _isr_declare(OFFLOAD_SW_IRQ, 0, offload_sw_irq_handler, NULL); z_arch_irq_enable(OFFLOAD_SW_IRQ); posix_sw_set_pending_IRQ(OFFLOAD_SW_IRQ); z_arch_irq_disable(OFFLOAD_SW_IRQ); } |