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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 | /* * Copyright (c) 2017, NXP * * SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv7-m.dtsi> #include <dt-bindings/clock/imx_ccm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/i2c/i2c.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m7"; reg = <0>; }; }; soc { flexram0: flexram@400b0000 { compatible = "nxp,imx-flexram"; reg = <0x400b0000 0x4000>; interrupts = <38 0>; #address-cells = <1>; #size-cells = <1>; itcm0: itcm@0 { compatible = "nxp,imx-itcm"; reg = <0x00000000 0x20000>; }; dtcm0: dtcm@20000000 { compatible = "nxp,imx-dtcm"; reg = <0x20000000 0x20000>; }; ocram0: ocram@20200000 { compatible = "mmio-sram"; reg = <0x20200000 0x40000>; }; }; flexspi0: flexspi0@402a8000 { compatible = "nxp,imx-flexspi"; reg = <0x402a8000 0x4000>; interrupts = <108 0>; label = "FLEXSPI0"; #address-cells = <1>; #size-cells = <0>; }; flexspi1: flexspi1@402a4000 { compatible = "nxp,imx-flexspi"; reg = <0x402a4000 0x4000>; interrupts = <107 0>; label = "FLEXSPI1"; #address-cells = <1>; #size-cells = <0>; }; semc0: semc0@402f0000 { compatible = "nxp,imx-semc"; reg = <0x402f0000 0x4000>; interrupts = <109 0>; label = "SEMC0"; #address-cells = <1>; #size-cells = <1>; }; ccm: ccm@400fc000 { compatible = "nxp,imx-ccm"; reg = <0x400fc000 0x4000>; label = "CCM"; clock-controller; #clock-cells = <3>; }; gpio1: gpio@401b8000 { compatible = "nxp,imx-gpio"; reg = <0x401b8000 0x4000>; interrupts = <80 0>, <81 0>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; }; gpio2: gpio@401bc000 { compatible = "nxp,imx-gpio"; reg = <0x401bc000 0x4000>; interrupts = <82 0>, <83 0>; label = "GPIO_2"; gpio-controller; #gpio-cells = <2>; }; gpio3: gpio@401c0000 { compatible = "nxp,imx-gpio"; reg = <0x401c0000 0x4000>; interrupts = <84 0>, <85 0>; label = "GPIO_3"; gpio-controller; #gpio-cells = <2>; }; gpio4: gpio@401c4000 { compatible = "nxp,imx-gpio"; reg = <0x401c4000 0x4000>; interrupts = <86 0>, <87 0>; label = "GPIO_4"; gpio-controller; #gpio-cells = <2>; }; gpio5: gpio@400c0000 { compatible = "nxp,imx-gpio"; reg = <0x400c0000 0x4000>; interrupts = <88 0>, <89 0>; label = "GPIO_5"; gpio-controller; #gpio-cells = <2>; }; i2c1: i2c@403f0000 { compatible = "nxp,imx-lpi2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x403f0000 0x4000>; interrupts = <28 0>; clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>; label = "I2C_1"; status = "disabled"; }; i2c2: i2c@403f4000 { compatible = "nxp,imx-lpi2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x403f4000 0x4000>; interrupts = <29 0>; clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>; label = "I2C_2"; status = "disabled"; }; i2c3: i2c@403f8000 { compatible = "nxp,imx-lpi2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x403f8000 0x4000>; interrupts = <30 0>; clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>; label = "I2C_3"; status = "disabled"; }; i2c4: i2c@403fc000 { compatible = "nxp,imx-lpi2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x403fc000 0x4000>; interrupts = <31 0>; clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>; label = "I2C_4"; status = "disabled"; }; iomuxc: iomuxc@401f8000 { reg = <0x401f8000 0x4000>; label = "PINMUX_0"; }; lcdif1: display-controller@402b8000 { compatible = "fsl,imx6sx-lcdif"; reg = <0x402b8000 0x4000>; interrupts = <42 0>; label = "ELCDIF_1"; status = "disabled"; }; spi1: spi@40394000 { compatible = "nxp,imx-lpspi"; reg = <0x40394000 0x4000>; interrupts = <32 3>; label = "SPI_1"; status = "disabled"; clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>; #address-cells = <1>; #size-cells = <0>; }; spi2: spi@40398000 { compatible = "nxp,imx-lpspi"; reg = <0x40398000 0x4000>; interrupts = <33 3>; label = "SPI_2"; status = "disabled"; clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>; #address-cells = <1>; #size-cells = <0>; }; spi3: spi@4039c000 { compatible = "nxp,imx-lpspi"; reg = <0x4039c000 0x4000>; interrupts = <34 3>; label = "SPI_3"; status = "disabled"; clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>; #address-cells = <1>; #size-cells = <0>; }; spi4: spi@403a0000 { compatible = "nxp,imx-lpspi"; reg = <0x403a0000 0x4000>; interrupts = <35 3>; label = "SPI_4"; status = "disabled"; clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>; #address-cells = <1>; #size-cells = <0>; }; uart1: uart@40184000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40184000 0x4000>; interrupts = <20 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>; label = "UART_1"; status = "disabled"; }; uart2: uart@40188000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40188000 0x4000>; interrupts = <21 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>; label = "UART_2"; status = "disabled"; }; uart3: uart@4018c000 { compatible = "nxp,kinetis-lpuart"; reg = <0x4018c000 0x4000>; interrupts = <22 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>; label = "UART_3"; status = "disabled"; }; uart4: uart@40190000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40190000 0x4000>; interrupts = <23 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>; label = "UART_4"; status = "disabled"; }; uart5: uart@40194000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40194000 0x4000>; interrupts = <24 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>; label = "UART_5"; status = "disabled"; }; uart6: uart@40198000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40198000 0x4000>; interrupts = <25 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>; label = "UART_6"; status = "disabled"; }; uart7: uart@4019c000 { compatible = "nxp,kinetis-lpuart"; reg = <0x4019c000 0x4000>; interrupts = <26 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>; label = "UART_7"; status = "disabled"; }; uart8: uart@401a0000 { compatible = "nxp,kinetis-lpuart"; reg = <0x401a0000 0x4000>; interrupts = <27 0>; clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>; label = "UART_8"; status = "disabled"; }; eth: ethernet@402d8000 { compatible = "nxp,kinetis-ethernet"; reg = <0x402D8000 0x628>; interrupts = <114 0>; interrupts-names = "COMMON"; status = "disabled"; local-mac-address = [00 00 00 00 00 00]; label = "ETH_0"; ptp { compatible = "nxp,kinetis-ptp"; status = "disabled"; interrupts = <115 0>; interrupts-names = "IEEE1588_TMR"; }; }; trng: random@400cc000 { compatible = "nxp,kinetis-trng"; reg = <0x400cc000 0x4000>; status = "ok"; interrupts = <53 0>; label = "TRNG"; }; }; }; &nvic { arm,num-irq-priority-bits = <4>; }; |