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Elixir Cross Referencer

# ARC EM4 options

#
# Copyright (c) 2014 Wind River Systems, Inc.
#
# SPDX-License-Identifier: Apache-2.0
#

menu "ARC Options"
	depends on ARC

config ARCH
	default "arc"

config ARCH_DEFCONFIG
	string
	default "arch/arc/defconfig"

menu "ARC EM4 processor options"

config	CPU_ARCEM4
	bool
	default y
	select CPU_ARCV2
	select ATOMIC_OPERATIONS_C
	help
	  This option signifies the use of an ARC EM4 CPU

endmenu

menu "ARCv2 Family Options"

config	CPU_ARCV2
	bool
	select ARCH_HAS_STACK_PROTECTION
	select ARCH_HAS_USERSPACE if ARC_CORE_MPU
	default y
	help
	  This option signifies the use of a CPU of the ARCv2 family.

config	DATA_ENDIANNESS_LITTLE
	bool
	default y
	help
	  This is driven by the processor implementation, since it is fixed in
	  hardware. The BSP should set this value to 'n' if the data is
	  implemented as big endian.

config	NUM_IRQ_PRIO_LEVELS
	int "Number of supported interrupt priority levels"
	range 1 16
	help
	  Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
	  The minimum value is 1.

	  The BSP must provide a valid default for proper operation.

config	NUM_IRQS
	int "Upper limit of interrupt numbers/IDs used"
	range 17 256
	help
	  Interrupts available will be 0 to NUM_IRQS-1.
	  The minimum value is 17 as the first 16 entries in the vector
	  table are for CPU exceptions.

	  The BSP must provide a valid default. This drives the size of the
	  vector table.

config	RGF_NUM_BANKS
	int "Number of General Purpose Register Banks"
	depends on CPU_ARCV2
	range 1 2
	default 2
	help
	  The ARC CPU can be configured to have more than one register
	  bank. If fast interrupts are supported (FIRQ), the 2nd
	  register bank, in the set, will be used by FIRQ interrupts.
	  If fast interrupts are supported but there is only 1
	  register bank, the fast interrupt handler must save
	  and restore general purpose registers.

config ARC_FIRQ
	bool "FIRQ enable"
	default y
	help
	  Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts
	  with highest priority, status32 and pc will be saved in aux regs,
	  other regs will be saved according to the number of register bank;
	  If FIRQ is disabled, the handle of interrupts with highest priority
	  will be same with other interrupts.

config	ARC_STACK_CHECKING
	bool
	default y if HW_STACK_PROTECTION
	select THREAD_STACK_INFO
	help
	  ARCV2 has a special feature allowing to check stack overflows. This
	  enables code that allows using this debug feature

config	FAULT_DUMP
	int "Fault dump level"
	default 2
	range 0 2
	help
	  Different levels for display information when a fault occurs.

	  2: The default. Display specific and verbose information. Consumes
		the most memory (long strings).

	  1: Display general and short information. Consumes less memory
		(short strings).

	  0: Off.

config	XIP
	default y if !UART_NSIM

config GEN_ISR_TABLES
	default y

config GEN_IRQ_START_VECTOR
	default 16

config HARVARD
	bool "Harvard Architecture"
	help
	  The ARC CPU can be configured to have two busses;
	  one for instruction fetching and another that serves as a data bus.

config CODE_DENSITY
	bool "Code Density Option"
	help
	  Enable code density option to get better code density

config ARC_HAS_SECURE
	bool
	#  a hidden option
	help
	  This option is enabled when ARC core supports secure mode

menu "ARC MPU Options"
depends on CPU_HAS_MPU

config ARC_MPU_ENABLE
	bool "Enable MPU"
	depends on CPU_HAS_MPU
	select ARC_MPU
	help
	  Enable MPU

source "arch/arc/core/mpu/Kconfig"

endmenu

config CACHE_LINE_SIZE_DETECT
	bool "Detect d-cache line size at runtime"
	help
	  This option enables querying the d-cache build register for finding
	  the d-cache line size at the expense of taking more memory and code
	  and a slightly increased boot time.

	  If the CPU's d-cache line size is known in advance, disable this
	  option and manually enter the value for CACHE_LINE_SIZE.

config CACHE_LINE_SIZE
	int "Cache line size" if !CACHE_LINE_SIZE_DETECT
	default 32
	help
	  Size in bytes of a CPU d-cache line.

	  Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.

config ARCH_CACHE_FLUSH_DETECT
	bool

config CACHE_FLUSHING
	bool "Enable d-cache flushing mechanism"
	help
	  This links in the sys_cache_flush() function, which provides a
	  way to flush multiple lines of the d-cache.
	  If the d-cache is present, set this to y.
	  If the d-cache is NOT present, set this to n.

endmenu

endmenu