Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 | /*
* Copyright (c) 2013-2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the Quark X1000 SoC
*
* This header file is used to specify and describe SoC-level aspects for
* the Quark X1000 SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <misc/util.h>
#ifndef _ASMLANGUAGE
#include <device.h>
#include <random/rand32.h>
#endif
#ifdef CONFIG_IOAPIC
#include <drivers/ioapic.h>
#endif
/*
* Ethernet (DesignWare)
*/
#define ETH_DW_PCI_VENDOR_ID 0x8086
#define ETH_DW_PCI_DEVICE_ID 0x0937
#define ETH_DW_PCI_CLASS 0x02
#define ETH_DW_0_BASE_ADDR 0x90002000
#define ETH_DW_0_IRQ 18
#define ETH_DW_0_PCI_BUS 0
#define ETH_DW_0_PCI_DEV 20
#define ETH_DW_0_PCI_FUNCTION 6
#define ETH_DW_0_PCI_BAR 0
/*
* SPI
*/
#define SPI_INTEL_VENDOR_ID 0x8086
#define SPI_INTEL_DEVICE_ID 0x935
#define SPI_INTEL_CLASS 0x0C
#define SPI_INTEL_PORT_0_REGS 0x90009000
#define SPI_INTEL_PORT_0_IRQ 16
#define SPI_INTEL_PORT_0_BUS 0
#define SPI_INTEL_PORT_0_DEV 21
#define SPI_INTEL_PORT_0_FUNCTION 0
#define SPI_INTEL_PORT_1_REGS 0x90008000
#define SPI_INTEL_PORT_1_IRQ 17
#define SPI_INTEL_PORT_1_BUS 0
#define SPI_INTEL_PORT_1_DEV 21
#define SPI_INTEL_PORT_1_FUNCTION 1
#define SPI_INTEL_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH)
/*
* GPIO
*/
#define GPIO_SCH_LEGACY_IO_PORTS_ACCESS
#define GPIO_SCH_0_BASE_ADDR 0x1080
#define GPIO_SCH_0_BITS 2
#define GPIO_SCH_1_BASE_ADDR 0x10A0
#define GPIO_SCH_1_BITS 6
#define GPIO_DW_PCI_VENDOR_ID 0x8086
#define GPIO_DW_PCI_DEVICE_ID 0x0934
#define GPIO_DW_PCI_CLASS 0x0C
#define GPIO_DW_0_BASE_ADDR 0x90006000
#define GPIO_DW_0_IRQ 18
#define GPIO_DW_0_BITS 8
#define GPIO_DW_0_PCI_BUS 0
#define GPIO_DW_0_PCI_DEV 21
#define GPIO_DW_0_PCI_FUNCTION 2
#define GPIO_DW_0_PCI_BAR 1
#if defined(CONFIG_IOAPIC)
#define GPIO_DW_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
#endif
/*
* I2C
*/
#define I2C_DW_0_PCI_VENDOR_ID 0x8086
#define I2C_DW_0_PCI_DEVICE_ID 0x0934
#define I2C_DW_0_PCI_CLASS 0x0C
#define I2C_DW_0_PCI_BUS 0
#define I2C_DW_0_PCI_DEV 21
#define I2C_DW_0_PCI_FUNCTION 2
#define I2C_DW_0_PCI_BAR 0
/*
* UART
*/
#define UART_NS16550_PORT_0_PCI_CLASS 0x07
#define UART_NS16550_PORT_0_PCI_BUS 0
#define UART_NS16550_PORT_0_PCI_DEV 20
#define UART_NS16550_PORT_0_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_0_PCI_DEVICE_ID 0x0936
#define UART_NS16550_PORT_0_PCI_FUNC 1
#define UART_NS16550_PORT_0_PCI_BAR 0
#define UART_NS16550_PORT_1_PCI_CLASS 0x07
#define UART_NS16550_PORT_1_PCI_BUS 0
#define UART_NS16550_PORT_1_PCI_DEV 20
#define UART_NS16550_PORT_1_PCI_VENDOR_ID 0x8086
#define UART_NS16550_PORT_1_PCI_DEVICE_ID 0x0936
#define UART_NS16550_PORT_1_PCI_FUNC 5
#define UART_NS16550_PORT_1_PCI_BAR 0
#ifdef CONFIG_IOAPIC
#define UART_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
#endif /* CONFIG_IOAPIC */
#ifdef __cplusplus
extern "C" {
#endif
#define NUM_STD_IRQS 16 /* number of "standard" IRQs on an x86 platform */
#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
/*
* The IRQ_CONNECT() API connects to a (virtualized) IRQ and the
* associated interrupt controller is programmed with the allocated vector.
* The Quark board virtualizes IRQs as follows:
*
* - The first CONFIG_IOAPIC_NUM_RTES IRQs are provided by the IOAPIC
* - The remaining IRQs are provided by the LOAPIC.
*
* Thus, for example, if the IOAPIC supports 24 IRQs:
*
* - IRQ0 to IRQ23 map to IOAPIC IRQ0 to IRQ23
* - IRQ24 to IRQ29 map to LOAPIC LVT entries as follows:
*
* IRQ24 -> LOAPIC_TIMER
* IRQ25 -> LOAPIC_THERMAL
* IRQ26 -> LOAPIC_PMC
* IRQ27 -> LOAPIC_LINT0
* IRQ28 -> LOAPIC_LINT1
* IRQ29 -> LOAPIC_ERROR
*/
/* PCI definitions */
#define PCI_BUS_NUMBERS 2
#define PCI_CTRL_ADDR_REG 0xCF8
#define PCI_CTRL_DATA_REG 0xCFC
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
/**
*
* @brief Convert PCI interrupt PIN to IRQ
*
* The routine uses "standard design consideration" and implies that
* INTA (pin 1) -> IRQ 16
* INTB (pin 2) -> IRQ 17
* INTC (pin 3) -> IRQ 18
* INTD (pin 4) -> IRQ 19
*
* In case a mini-PCIe card is used, the IRQs are swizzled:
* INTA (pin 1) -> IRQ 17
* INTB (pin 2) -> IRQ 18
* INTC (pin 3) -> IRQ 19
* INTD (pin 4) -> IRQ 16
*
* @return IRQ number, -1 if the result is incorrect
*
*/
static inline int pci_pin2irq(int bus, int dev, int pin)
{
ARG_UNUSED(dev);
if (bus < 0 || bus > 1) {
return -1;
}
if ((pin < PCI_INTA) || (pin > PCI_INTD)) {
return -1;
}
return NUM_STD_IRQS + ((pin - 1 + bus) & 3);
}
#ifdef __cplusplus
}
#endif
#endif /* __SOC_H_ */
|