/*
 * Copyright (c) 2017 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
#include <dt-bindings/i2c/i2c.h>

#define __SIZE_K(x) (x * 1024)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "quark_x1000";
			reg = <0>;
		};

		intc: ioapic@fec00000  {
			compatible = "intel,ioapic";
			reg = <0xfec00000 0x100000>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};

	flash0: flash@100000{
		reg = <0x00100000 DT_FLASH_SIZE>;
	};

	sram0: memory@400000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x00400000 DT_SRAM_SIZE>;
	};


	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;


		uart0: uart@9000f000 {
			compatible = "ns16550";
			reg = <0x9000f000 0x400>;
			label = "UART_0";
			clock-frequency = <44236800>;
			interrupts = <0 IRQ_TYPE_LEVEL_LOW 0>;
			interrupt-parent = <&intc>;

			status = "disabled";
		};

		uart1: uart@9000b000 {
			compatible = "ns16550";
			reg = <0x9000b000 0x400>;
			label = "UART_1";
			clock-frequency = <44236800>;
			interrupts = <17 IRQ_TYPE_LEVEL_LOW 3>;
			interrupt-parent = <&intc>;

			status = "disabled";
		};

		i2c0: i2c@90007000 {
			compatible = "snps,designware-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x90007000 0x400>;
			interrupts = <18 IRQ_TYPE_LEVEL_LOW 2>;
			interrupt-parent = <&intc>;
			label = "I2C_0";

			status = "disabled";
		};
	};
};