#include <arm/armv7-m.dtsi>

#include <ti/mem.h>
#include <dt-bindings/i2c/i2c.h>

#define INT_UARTA0              21          // UART0 Rx and Tx
#define INT_UARTA1              22          // UART1 Rx and Tx
#define INT_I2CA0               24          // I2C controller

/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
/* which are offset by 16: */
#define EXP_UARTA0 (INT_UARTA0 - 16)
#define EXP_UARTA1 (INT_UARTA1 - 16)
#define EXP_I2CA0  (INT_I2CA0 - 16)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4";
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <DT_SRAM_START DT_SRAM_SIZE>;
	};

	flash0: serial-flash@0 {
		compatible = "serial-flash";
		reg = <0x0 DT_SFLASH_SIZE>;
	};

#if defined(CONFIG_SOC_CC3220SF)
	flash1: flash@1000000 {
		compatible = "soc-nv-flash";
		label = "FLASH_1";
		reg = <0x01000000 DT_FLASH_SIZE>;
	};
#endif

	soc {
		uart0: uart@4000C000 {
			compatible = "ti,cc32xx-uart";
			reg = <0x4000C000 0x4c>;
			interrupts = <EXP_UARTA0 3>;
			status = "disabled";
			label = "UART_0";
		};

		uart1: uart@4000D000 {
			compatible = "ti,cc32xx-uart";
			reg = <0x4000D000 0x4c>;
			interrupts = <EXP_UARTA1 3>;
			status = "disabled";
			label = "UART_1";
		};

		i2c0: i2c@40020000 {
			compatible = "ti,cc32xx-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40020000 0xfc8>;
			interrupts = <EXP_I2CA0 3>;
			status = "disabled";
			label= "I2C_0";
		};

	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};