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/* * Copyright (c) 2017 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ #include <st/stm32l4.dtsi> / { soc { pinctrl: pin-controller@48000000 { gpiod: gpio@48000c00 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; label = "GPIOD"; }; gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; label = "GPIOE"; }; gpiof: gpio@48001400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; label = "GPIOF"; }; gpiog: gpio@48001800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; label = "GPIOG"; }; }; uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; interrupts = <52 0>; status = "disabled"; label = "UART_4"; }; uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; interrupts = <53 0>; status = "disabled"; label = "UART_5"; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_2"; }; i2c3: i2c@40005C00 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005C00 0x400>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_3"; }; spi3: spi@40003C00 { compatible = "st,stm32-spi-fifo"; #address-cells = <1>; #size-cells = <0>; reg = <0x40003C00 0x400>; interrupts = <51 5>; status = "disabled"; label = "SPI_3"; }; }; }; |