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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 | /* * Copyright (c) 2017 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv7-m.dtsi> #include <st/stm32f4-pinctrl.dtsi> #include <st/mem.h> #include <dt-bindings/clock/stm32_clock.h> #include <dt-bindings/i2c/i2c.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4f"; reg = <0>; }; }; sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x20000000 DT_SRAM_SIZE>; }; soc { flash-controller@40023c00 { compatible = "st,stm32f4-flash-controller"; label = "FLASH_CTRL"; reg = <0x40023c00 0x400>; interrupts = <4 0>; #address-cells = <1>; #size-cells = <1>; flash0: flash@8000000 { compatible = "soc-nv-flash"; label = "FLASH_STM32"; reg = <0x08000000 DT_FLASH_SIZE>; write-block-size = <1>; }; }; rcc: rcc@40023800 { compatible = "st,stm32-rcc"; clocks-controller; #clocks-cells = <2>; reg = <0x40023800 0x400>; label = "STM32_CLK_RCC"; }; pinctrl: pin-controller { compatible = "st,stm32-pinmux"; #address-cells = <1>; #size-cells = <1>; reg = <0x40020000 0x1C00>; }; usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; interrupts = <37 0>; status = "disabled"; label = "UART_1"; }; usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; interrupts = <38 0>; status = "disabled"; label = "UART_2"; }; usart6: serial@40011400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>; interrupts = <71 0>; status = "disabled"; label = "UART_6"; }; i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v1"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_1"; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v1"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_2"; }; i2c3: i2c@40005C00 { compatible = "st,stm32-i2c-v1"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005C00 0x400>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_3"; }; spi1: spi@40013000 { compatible = "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; interrupts = <35 5>; status = "disabled"; label = "SPI_1"; }; usbotg_fs: usb@50000000 { compatible = "st,stm32-otgfs"; reg = <0x50000000 0x40000>; interrupts = <67 0>; interrupt-names = "otgfs"; num-bidir-endpoints = <1>; num-in-endpoints = <3>; num-out-endpoints = <3>; ram-size = <1280>; status = "disabled"; label= "OTGFS"; }; }; }; &nvic { arm,num-irq-priority-bits = <4>; }; |