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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 | /** * @file * * @brief Public APIs for the DMA drivers. */ /* * Copyright (c) 2016 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ #ifndef _DMA_H_ #define _DMA_H_ #include <kernel.h> #include <device.h> #ifdef __cplusplus extern "C" { #endif /** * @brief DMA Interface * @defgroup DMA_interface DMA Interface * @ingroup io_interfaces * @{ */ enum dma_channel_direction { MEMORY_TO_MEMORY = 0x0, MEMORY_TO_PERIPHERAL, PERIPHERAL_TO_MEMORY }; /** * @brief DMA block configuration structure. * * source_address is block starting address at source * source_gather_interval is the address adjustment at gather boundary * dest_address is block starting address at destination * dest_scatter_interval is the address adjustment at scatter boundary * dest_scatter_count is the continuous transfer count between scatter * boundaries * source_gather_count is the continuous transfer count between gather * boundaries * block_size is the number of bytes to be transferred for this block. * * config is a bit field with the following parts: * source_gather_en [ 0 ] - 0-disable, 1-enable * dest_scatter_en [ 1 ] - 0-disable, 1-enable * source_addr_adj [ 2 : 3 ] - 00-increment, 01-decrement, * 10-no change * dest_addr_adj [ 4 : 5 ] - 00-increment, 01-decrement, * 10-no change * source_reload_en [ 6 ] - reload source address at the end of * block transfer * 0-disable, 1-enable * dest_reload_en [ 7 ] - reload destination address at the end * of block transfer * 0-disable, 1-enable * fifo_mode_control [ 8 : 11 ] - How full of the fifo before transfer * start. HW specific. * flow_control_mode [ 12 ] - 0-source request served upon data * availability * 1-source request postponed until * destination request happens * reserved [ 13 : 15 ] */ struct dma_block_config { u32_t source_address; u32_t source_gather_interval; u32_t dest_address; u32_t dest_scatter_interval; u16_t dest_scatter_count; u16_t source_gather_count; u32_t block_size; struct dma_block_config *next_block; u16_t source_gather_en : 1; u16_t dest_scatter_en : 1; u16_t source_addr_adj : 2; u16_t dest_addr_adj : 2; u16_t source_reload_en : 1; u16_t dest_reload_en : 1; u16_t fifo_mode_control : 4; u16_t flow_control_mode : 1; u16_t reserved : 3; }; /** * @brief DMA configuration structure. * * dma_slot [ 0 : 5 ] - which peripheral and direction * (HW specific) * channel_direction [ 6 : 8 ] - 000-memory to memory, 001-memory to * peripheral, 010-peripheral to memory, * ... * complete_callback_en [ 9 ] - 0-callback invoked at completion only * 1-callback invoked at completion of * each block * error_callback_en [ 10 ] - 0-error callback enabled * 1-error callback disabled * source_handshake [ 11 ] - 0-HW, 1-SW * dest_handshake [ 12 ] - 0-HW, 1-SW * channel_priority [ 13 : 16 ] - DMA channel priority * source_chaining_en [ 17 ] - enable/disable source block chaining * 0-disable, 1-enable * dest_chaining_en [ 18 ] - enable/disable destination block * chaining. * 0-disable, 1-enable * reserved [ 19 : 31 ] * * source_data_size [ 0 : 15 ] - width of source data (in bytes) * dest_data_size [ 16 : 31 ] - width of dest data (in bytes) * source_burst_length [ 0 : 15 ] - number of source data units * dest_burst_length [ 16 : 31 ] - number of destination data units * * block_count is the number of blocks used for block chaining, this * depends on availability of the DMA controller. * * dma_callback is the callback function pointer. If enabled, callback function * will be invoked at transfer completion or when error happens * (error_code: zero-transfer success, non zero-error happens). */ struct dma_config { u32_t dma_slot : 6; u32_t channel_direction : 3; u32_t complete_callback_en : 1; u32_t error_callback_en : 1; u32_t source_handshake : 1; u32_t dest_handshake : 1; u32_t channel_priority : 4; u32_t source_chaining_en : 1; u32_t dest_chaining_en : 1; u32_t reserved : 13; u32_t source_data_size : 16; u32_t dest_data_size : 16; u32_t source_burst_length : 16; u32_t dest_burst_length : 16; u32_t block_count; struct dma_block_config *head_block; void (*dma_callback)(struct device *dev, u32_t channel, int error_code); }; /** * @cond INTERNAL_HIDDEN * * These are for internal use only, so skip these in * public documentation. */ typedef int (*dma_api_config)(struct device *dev, u32_t channel, struct dma_config *config); typedef int (*dma_api_start)(struct device *dev, u32_t channel); typedef int (*dma_api_stop)(struct device *dev, u32_t channel); struct dma_driver_api { dma_api_config config; dma_api_start start; dma_api_stop stop; }; /** * @endcond */ /** * @brief Configure individual channel for DMA transfer. * * @param dev Pointer to the device structure for the driver instance. * @param channel Numeric identification of the channel to configure * @param config Data structure containing the intended configuration for the * selected channel * * @retval 0 if successful. * @retval Negative errno code if failure. */ static inline int dma_config(struct device *dev, u32_t channel, struct dma_config *config) { const struct dma_driver_api *api = dev->driver_api; return api->config(dev, channel, config); } /** * @brief Enables DMA channel and starts the transfer, the channel must be * configured beforehand. * * @param dev Pointer to the device structure for the driver instance. * @param channel Numeric identification of the channel where the transfer will * be processed * * @retval 0 if successful. * @retval Negative errno code if failure. */ static inline int dma_start(struct device *dev, u32_t channel) { const struct dma_driver_api *api = dev->driver_api; return api->start(dev, channel); } /** * @brief Stops the DMA transfer and disables the channel. * * @param dev Pointer to the device structure for the driver instance. * @param channel Numeric identification of the channel where the transfer was * being processed * * @retval 0 if successful. * @retval Negative errno code if failure. */ static inline int dma_stop(struct device *dev, u32_t channel) { const struct dma_driver_api *api = dev->driver_api; return api->stop(dev, channel); } /** * @brief Look-up generic width index to be used in registers * * WARNING: This look-up works for most controllers, but *may* not work for * yours. Ensure your controller expects the most common register * bit values before using this convenience function. If your * controller does not support these values, you will have to write * your own look-up inside the controller driver. * * @param size: width of bus (in bytes) * * @retval common DMA index to be placed into registers. */ static inline u32_t dma_width_index(u32_t size) { /* Check boundaries (max supported width is 32 Bytes) */ if (size < 1 || size > 32) { return 0; /* Zero is the default (8 Bytes) */ } /* Ensure size is a power of 2 */ if (!is_power_of_two(size)) { return 0; /* Zero is the default (8 Bytes) */ } /* Convert to bit pattern for writing to a register */ return find_msb_set(size); } /** * @brief Look-up generic burst index to be used in registers * * WARNING: This look-up works for most controllers, but *may* not work for * yours. Ensure your controller expects the most common register * bit values before using this convenience function. If your * controller does not support these values, you will have to write * your own look-up inside the controller driver. * * @param burst: number of bytes to be sent in a single burst * * @retval common DMA index to be placed into registers. */ static inline u32_t dma_burst_index(u32_t burst) { /* Check boundaries (max supported burst length is 256) */ if (burst < 1 || burst > 256) { return 0; /* Zero is the default (1 burst length) */ } /* Ensure burst is a power of 2 */ if (!(burst & (burst - 1))) { return 0; /* Zero is the default (1 burst length) */ } /* Convert to bit pattern for writing to a register */ return find_msb_set(burst); } /** * @} */ #ifdef __cplusplus } #endif #endif /* _DMA_H_ */ |