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#include <arm/armv7-m.dtsi> #include <nordic/mem.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4f"; reg = <0>; }; }; flash-controller@4001E000 { compatible = "nrf,nrf52-flash-controller"; reg = <0x4001E000 0x550>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; reg = <0x00000000 DT_FLASH_SIZE>; write-block-size = <4>; }; }; sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x20000000 DT_SRAM_SIZE>; }; soc { uart0: uart@40002000 { compatible = "nordic,nrf-uarte", "nordic,nrf-uart"; reg = <0x40002000 0x1000>; interrupts = <2 1>; status = "disabled"; label = "UART_0"; }; uart1: uart@40028000 { compatible = "nordic,nrf-uarte"; reg = <0x40028000 0x1000>; interrupts = <40 1>; status = "disabled"; label = "UART_1"; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; |