Boot Linux faster!

Check our new training course

Boot Linux faster!

Check our new training course
and Creative Commons CC-BY-SA
lecture and lab materials

Bootlin logo

Elixir Cross Referencer

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
# Kconfig - Quark SE configuration options

#
# Copyright (c) 2015 Intel Corp.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#

if SOC_QUARK_SE
config SOC
        default quark_se

config  PHYS_RAM_ADDR
	default 0xA8006400

config  PHYS_LOAD_ADDR
	default 0x40030000 if XIP

config RAM_SIZE
        default 55

config ROM_SIZE
        default 144

config	SYS_CLOCK_HW_CYCLES_PER_SEC
	default 32000000

config IOAPIC_NUM_RTES
	default 64

config LOAPIC_TIMER_IRQ
	default 64

config EOI_FORWARDING_BUG
	bool
	default y
	help
	Quark SE LOAPIC has issues with forwarding EOI to the IOAPIC for level
	triggered interrupts, this is a SW workaround.


config TOOLCHAIN_VARIANT
	default "iamcu"

if PINMUX
config PINMUX_BASE
        default 0xb0800900

endif

config AIO_DW_COMPARATOR_BASE_ADDR
	hex
	depends on AIO_DW_COMPARATOR
	default 0xb0800300

config ARC_INIT
	bool "Quark SE ARC Kickoff"
	default n
	help
	Allows x86 processor to kickoff the ARC slave processor.

config ARC_INIT_DEBUG
	bool "Allows the usage of GDB with the ARC processor."
	depends on ARC_INIT
	default n
	help
	This option will stop the master processor from boot-strapping
	the ARC slave processor. This will allow GDB to halt and
	engage the ARC processor to proceed step by step execution.

if GPIO
config GPIO_DW
	def_bool y

if GPIO_DW
config GPIO_DW_BOTHEDGES_SUPPORT
	def_bool y
config GPIO_DW_CLOCK_GATE
	def_bool n
config GPIO_DW_CLOCK_GATE_DRV_NAME
	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME

config GPIO_DW_0
	def_bool y
config GPIO_DW_0_BASE_ADDR
	default 0xb0000C00
config GPIO_DW_0_IRQ
	default 8
config GPIO_DW_0_PRI
	default 2
config GPIO_DW_0_BITS
	default 32
config GPIO_DW_0_CLOCK_GATE_SUBSYS
	default 13
	depends on GPIO_DW_CLOCK_GATE

config GPIO_DW_1
	def_bool y
config GPIO_DW_1_BASE_ADDR
	default 0xb0800b00
config GPIO_DW_1_IRQ
	default 31
config GPIO_DW_1_PRI
	default 2
config GPIO_DW_1_BITS
	default 6
endif

if QMSI_DRIVERS
config GPIO_QMSI
	def_bool n
if GPIO_QMSI
config GPIO_QMSI_0
	def_bool n
config GPIO_QMSI_0_IRQ
	default 8
config GPIO_QMSI_0_PRI
	default 2
config GPIO_QMSI_AON
	def_bool n
config GPIO_QMSI_AON_NAME
	default "gpio_aon"
config GPIO_QMSI_AON_IRQ
	default 31
config GPIO_QMSI_AON_PRI
	default 2
endif
endif
endif

if I2C
config I2C_DW
	def_bool y

if I2C_DW
config I2C_DW_0
        def_bool y
config I2C_DW_0_BASE
        default 0xb0002800
config I2C_DW_0_NAME
        default "I2C0"
config I2C_DW_0_IRQ
	default 0
config I2C_DW_0_INT_PRIORITY
	default 2

config I2C_DW_1
        def_bool y
config I2C_DW_1_BASE
        default 0xb0002c00
config I2C_DW_1_NAME
        default "I2C1"
config I2C_DW_1_IRQ
	default 1
config I2C_DW_1_INT_PRIORITY
	default 2
endif # I2C_DW

if I2C_QMSI
config I2C_QMSI_0
	def_bool y
config I2C_QMSI_0_IRQ
	default 0
config I2C_QMSI_0_INT_PRIORITY
	default 2

config I2C_QMSI_1
	def_bool y
config I2C_QMSI_1_IRQ
	default 1
config I2C_QMSI_1_INT_PRIORITY
	default 2
endif # I2C_QMSI
endif # I2C

if CLOCK_CONTROL
config CLOCK_CONTROL_QUARK_SE
	def_bool y

config CLOCK_CONTROL_QUARK_SE_PERIPHERAL
	def_bool y
config CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
	default "clk_peripheral"

config  CLOCK_CONTROL_QUARK_SE_EXTERNAL
       def_bool y
config CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME
	default "clk_external"

config  CLOCK_CONTROL_QUARK_SE_SENSOR
       def_bool y
config CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME
	default "clk_sensor"
endif

if SPI
config SPI_DW
	def_bool y
if SPI_DW
config SPI_DW_CLOCK_GATE
	def_bool n
config SPI_DW_CLOCK_GATE_DRV_NAME
	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME

config SPI_DW_PORT_0
	def_bool y
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
	default 14
	depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_0_REGS
	default 0xb0001000
config SPI_DW_PORT_0_IRQ
	default 2
config SPI_DW_PORT_0_PRI
	default 2

config SPI_DW_PORT_1
	def_bool y
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
	default 15
	depends on SPI_DW_CLOCK_GATE
config SPI_DW_PORT_1_REGS
	default 0xb0001400
config SPI_DW_PORT_1_IRQ
	default 3
config SPI_DW_PORT_1_PRI
	default 2
endif # SPI_DW

config SPI_QMSI
       def_bool n

if SPI_QMSI
config SPI_QMSI_PORT_0
	def_bool y
config SPI_QMSI_PORT_0_IRQ
	default 2
config SPI_QMSI_PORT_0_PRI
	default 2
config SPI_QMSI_PORT_1
	def_bool y
config SPI_QMSI_PORT_1_IRQ
	default 3
config SPI_QMSI_PORT_1_PRI
	default 2
endif # SPI_QMSI
endif

if WATCHDOG
config WDT_DW
	def_bool y

if WDT_DW
config WDT_DW_CLOCK_GATE
	def_bool n
config WDT_DW_CLOCK_GATE_DRV_NAME
	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config WDT_DW_CLOCK_GATE_SUBSYS
	default 10
config WDT_DW_BASE_ADDR
	default 0xB0000000
config WDT_DW_IRQ
	default 12
config WDT_DW_IRQ_PRI
	default 2
endif # WDT_DW

if WDT_QMSI
config WDT_QMSI_IRQ
	default 12
config WDT_QMSI_IRQ_PRI
	default 2
endif # WDT_QMSI
endif # WATCHDOG

if RTC
config RTC_IRQ
	default 11
config RTC_IRQ_PRI
	default 2
config RTC_DW
	def_bool y

if RTC_DW
config RTC_DW_CLOCK_GATE
	def_bool y
config RTC_DW_CLOCK_GATE_DRV_NAME
	default CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME
config RTC_DW_CLOCK_GATE_SUBSYS
	default 11
config RTC_DW_BASE_ADDR
	default 0xB0000400
endif # RTC_DW
endif # RTC

config KERNEL_INIT_PRIORITY_DEFAULT
	default 40

config KERNEL_INIT_PRIORITY_DEVICE
	default 50

config UART_CONSOLE_PRIORITY
	default 60

config IPM_CONSOLE_PRIORITY
	default 60

config GPIO_DW_INIT_PRIORITY
	default 60

config I2C_INIT_PRIORITY
	default 60

config SPI_DW_INIT_PRIORITY
	default 70 # It might require GPIO to be ready first

if UART_NS16550

config UART_NS16550_PORT_0
	def_bool y

if UART_NS16550_PORT_0

config UART_NS16550_PORT_0_NAME
	default "UART_0"
config UART_NS16550_PORT_0_BASE_ADDR
	default 0xB0002000
config UART_NS16550_PORT_0_IRQ
	default 5
config UART_NS16550_PORT_0_IRQ_PRI
	default 3
config UART_NS16550_PORT_0_BAUD_RATE
	default 115200
config UART_NS16550_PORT_0_CLK_FREQ
	default 32000000
config UART_NS16550_PORT_0_OPTIONS
	default 0

endif # UART_NS16550_PORT_0

config UART_NS16550_PORT_1
	def_bool y

if UART_NS16550_PORT_1

config UART_NS16550_PORT_1_NAME
	default "UART_1"
config UART_NS16550_PORT_1_BASE_ADDR
	default 0xB0002400
config UART_NS16550_PORT_1_IRQ
	default 6
config UART_NS16550_PORT_1_IRQ_PRI
	default 3
config UART_NS16550_PORT_1_BAUD_RATE
	default 115200
config UART_NS16550_PORT_1_CLK_FREQ
	default 32000000
config UART_NS16550_PORT_1_OPTIONS
	default 0

endif # UART_NS16550_PORT_1

endif # UART_NS16550

if UART_CONSOLE

config UART_CONSOLE_ON_DEV_NAME
	default "UART_1"
config UART_CONSOLE_IRQ
	default 6
config UART_CONSOLE_IRQ_PRI
	default 3

endif

if BLUETOOTH_UART

config BLUETOOTH_UART_ON_DEV_NAME
	default "UART_1"
config BLUETOOTH_UART_IRQ
	default 38
config BLUETOOTH_UART_IRQ_PRI
	default 3

endif

if PWM
if PWM_DW

config PWM_DW_BASE_ADDR
	default 0xB0000800

config PWM_DW_NUM_PORTS
	default 4

endif
endif

if IPM_CONSOLE_RECEIVER
config QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32
	int "IPM Console Ring Buffer Size"
	default 256
	help
	Size of the buffer for the console reciever, for incoming
	console messages from the ARC side. Must be a power of 2.
endif

endif #SOC_QUARK_SE_X86