# Kconfig - x86 general configuration options

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# Copyright (c) 2014-2015 Wind River Systems, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
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#     http://www.apache.org/licenses/LICENSE-2.0
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# distributed under the License is distributed on an "AS IS" BASIS,
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# See the License for the specific language governing permissions and
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menu "x86 architecture"
	depends on X86

config ARCH
        default "x86"

config X86_IAMCU
	bool
	default n
	prompt "IAMCU calling convention"
	help
	The IAMCU calling convention changes the X86 C calling convention to
	pass some arguments via registers allowing for code size and performance
	improvements.  Great care needs to be taken if you have assembly code
	that will be called from C or C code called from assembly code, the
	assembly code will need to be updated to conform to the new calling
	convention.  If in doubt say N

config ARCH_DEFCONFIG
	string
	default "arch/x86/defconfig"


source "arch/x86/core/Kconfig"

choice
prompt "SoC Selection"
source "arch/x86/soc/*/Kconfig.soc"
endchoice

choice
prompt "Intel Processor"
default CPU_MINUTEIA

config CPU_ATOM
	bool "Atom"
	select CMOV
	select CPU_MIGHT_SUPPORT_CLFLUSH if CACHE_FLUSHING
	help
	This option signifies the use of a CPU from the Atom family.

config CPU_MINUTEIA
	bool "Minute IA"
	select CPU_MIGHT_SUPPORT_CLFLUSH if CACHE_FLUSHING
	help
	This option signifies the use of a CPU from the Minute IA family.
endchoice


menu "Processor Capabilities"
menu "Floating Point Options"

config  FLOAT
	bool
	prompt "Floating point registers"
	default n
	help
	This option allows tasks and fibers to use the floating point registers.
	By default, only a single task or fiber may use the registers, and only
	the x87 FPU/MMX registers may be used.

	Disabling this option means that any task or fiber that uses a
	floating point register will get a fatal exception.

config  FP_SHARING
	bool
	prompt "Floating point register sharing"
	depends on FLOAT
	default n
	help
	This option allows multiple tasks and fibers to use the floating point
	registers. Any task that uses the floating point registers must provide
	stack space where the kernel can save these registers during context
	switches; a task that uses only the x87 FPU/MMX registers must provide
	108 bytes of added stack space, while a task the uses the SSE registers
	must provide 464 bytes of added stack space.

config  SSE
	bool
	prompt "SSE registers"
	depends on FLOAT
	default n
	help
	This option enables the use of SSE registers by tasks and fibers.

config SSE_FP_MATH
	bool
	prompt "Compiler-generated SSEx instructions"
	depends on SSE
	default n
	help
	This option allows the compiler to generate SSEx instructions for
	performing floating point math. This can greatly improve performance
	when exactly the same operations are to be performed on multiple
	data objects; however, it can also significantly reduce performance
	when pre-emptive task switches occur because of the larger register
	set that must be saved and restored.

	Disabling this option means that the compiler utilizes only the
	x87 instruction set for floating point operations.

choice
prompt "Reboot implementation"
depends on REBOOT
default REBOOT_RST_CNT

config REBOOT_RST_CNT
	bool
	prompt "Reboot via RST_CNT register"
	help
	Reboot via the RST_CNT register, going back to BIOS.

endchoice

endmenu

config ISA_IA32
	bool
	default y
	help
	This option signifies the use of a CPU based on the Intel IA-32
	instruction set architecture.

config IA32_LEGACY_IO_PORTS
	bool
	prompt "Support IA32 legacy IO ports"
	default n
	depends on ISA_IA32
	help
	This option enables IA32 legacy IO ports. Note these are much slower
	than memory access, so they should be used in last resort.

config CMOV
	def_bool n
	help
	This option signifies the use of an Intel CPU that supports
	the CMOV instruction.

config CACHE_LINE_SIZE_DETECT
	bool
	prompt "Detect cache line size at runtime"
	default y
	help
	This option enables querying the CPUID register for finding the cache line
	size at the expense of taking more memory and code and a slightly increased
	boot time.

	If the CPU's cache line size is known in advance, disable this option and
	manually enter the value for CACHE_LINE_SIZE.

config CACHE_LINE_SIZE
	int
	prompt "Cache line size" if !CACHE_LINE_SIZE_DETECT
	default 0 if CACHE_LINE_SIZE_DETECT
	default 64 if CPU_ATOM
	default 0
	help
	Size in bytes of a CPU cache line.

	Detect automatically at runtime by selecting CACHE_LINE_SIZE_DETECT.

config CPU_MIGHT_SUPPORT_CLFLUSH
	bool
	depends on CACHE_FLUSHING
	default n
	help
	If a platform uses a processor that possibly implements CLFLUSH, change
	the default in that platform's config file.

config CLFLUSH_INSTRUCTION_SUPPORTED
	bool
	prompt "CLFLUSH instruction supported" if CPU_MIGHT_SUPPORT_CLFLUSH
	depends on CPU_MIGHT_SUPPORT_CLFLUSH && !CLFLUSH_DETECT
	default n
	help
	An implementation of sys_cache_flush() that uses CLFLUSH is made
	available, instead of the one using WBINVD.

	This option should only be enabled if it is known in advance that the
	CPU supports the CLFLUSH instruction. It disables runtime detection of
	CLFLUSH support thereby reducing both memory footprint and boot time.

config CLFLUSH_DETECT
	bool
	prompt "Detect support of CLFLUSH instruction at runtime"
	depends on CPU_MIGHT_SUPPORT_CLFLUSH
	default y
	help
	This option should be enabled if it is not known in advance whether the
	CPU supports the CLFLUSH instruction or not.

	The CPU is queried at boot time to determine which of the multiple
	implementations of sys_cache_flush() linked into the image is the
	correct one to use.

	If the CPU's support (or lack thereof) of CLFLUSH is known in advance, then
	disable this option and set CLFLUSH_INSTRUCTION_SUPPORTED as appropriate.

config ARCH_CACHE_FLUSH_DETECT
	bool
	default y
	depends on CLFLUSH_DETECT

config CACHE_FLUSHING
	bool
	default n
	prompt "Enable cache flushing mechanism"
	help
	This links in the sys_cache_flush() function. A mechanism for flushing the
	cache must be selected as well. By default, that mechanism is discovered at
	runtime.
endmenu

menu "Platform Capabilities"
config ADVANCED_IDLE_SUPPORTED
	bool "Advanced Idle Supported"
	default n
	help
	This option signifies that the target supports the ADVANCED_IDLE
	configuration option.

config NUM_DYNAMIC_STUBS
	int "Number of dynamic int stubs"
	default 0
	help
	This option specifies the number of interrupt handlers that can be
	installed dynamically using irq_connect_dynamic().

config NUM_DYNAMIC_EXC_STUBS
	int "Number of dynamic exception stubs"
	default 0
	help
	This option specifies the maximum number of dynamically allocated
	exception stubs that are to be used with exceptions that push an
	error code onto the stack.

config NUM_DYNAMIC_EXC_NOERR_STUBS
	int "Number of dynamic no-error exception stubs"
	default 0
	help
	This option specifies the maximum number of dynamically allocated
	exception stubs that are to be used with exceptions that do not push
	an error code onto the stack.

config PIC_DISABLE
	bool "Disable PIC"
	default n
	help
	This option disables all interrupts on the PIC

config IRQ_OFFLOAD
	bool "Enable IRQ offload"
	default n
	help
	Enable irq_offload() API which allows functions to be synchronously
	run in interrupt context. Uses one entry in the	IDT.  Mainly useful
	for test cases.

config IRQ_OFFLOAD_VECTOR
	int "IDT vector to use for IRQ offload"
	default 63 if MVIC
	default 32
	range 32 255
	depends on IRQ_OFFLOAD
	help
	Specify the IDT vector to use for the IRQ offload interrupt handler.
	The default should be fine for most arches, but on systems like MVIC
	where there is a fixed IRQ-to-vector mapping another value may be
	needed to avoid collision.

config XIP
	default n
endmenu



source "arch/x86/soc/*/Kconfig"

endmenu