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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 | #ifndef __dma_defs_h
#define __dma_defs_h
/*
* This file is autogenerated from
* file: ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: dma_regdes.r,v 1.39 2005/02/10 14:07:23 janb Exp
* last modfied: Mon Apr 11 16:06:51 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile dma_defs.h ../../inst/dma/inst/dma_common/rtl/dma_regdes.r
* id: $Id: dma_defs.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope dma */
/* Register rw_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_data;
#define REG_RD_ADDR_dma_rw_data 0
#define REG_WR_ADDR_dma_rw_data 0
/* Register rw_data_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_next;
#define REG_RD_ADDR_dma_rw_data_next 4
#define REG_WR_ADDR_dma_rw_data_next 4
/* Register rw_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_buf;
#define REG_RD_ADDR_dma_rw_data_buf 8
#define REG_WR_ADDR_dma_rw_data_buf 8
/* Register rw_data_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int dummy1 : 2;
unsigned int out_eop : 1;
unsigned int intr : 1;
unsigned int wait : 1;
unsigned int dummy2 : 26;
} reg_dma_rw_data_ctrl;
#define REG_RD_ADDR_dma_rw_data_ctrl 12
#define REG_WR_ADDR_dma_rw_data_ctrl 12
/* Register rw_data_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 3;
unsigned int in_eop : 1;
unsigned int dummy2 : 28;
} reg_dma_rw_data_stat;
#define REG_RD_ADDR_dma_rw_data_stat 16
#define REG_WR_ADDR_dma_rw_data_stat 16
/* Register rw_data_md, scope dma, type rw */
typedef struct {
unsigned int md : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_data_md;
#define REG_RD_ADDR_dma_rw_data_md 20
#define REG_WR_ADDR_dma_rw_data_md 20
/* Register rw_data_md_s, scope dma, type rw */
typedef struct {
unsigned int md_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_data_md_s;
#define REG_RD_ADDR_dma_rw_data_md_s 24
#define REG_WR_ADDR_dma_rw_data_md_s 24
/* Register rw_data_after, scope dma, type rw */
typedef unsigned int reg_dma_rw_data_after;
#define REG_RD_ADDR_dma_rw_data_after 28
#define REG_WR_ADDR_dma_rw_data_after 28
/* Register rw_ctxt, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt;
#define REG_RD_ADDR_dma_rw_ctxt 32
#define REG_WR_ADDR_dma_rw_ctxt 32
/* Register rw_ctxt_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_next;
#define REG_RD_ADDR_dma_rw_ctxt_next 36
#define REG_WR_ADDR_dma_rw_ctxt_next 36
/* Register rw_ctxt_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int dummy1 : 3;
unsigned int intr : 1;
unsigned int dummy2 : 1;
unsigned int store_mode : 1;
unsigned int en : 1;
unsigned int dummy3 : 24;
} reg_dma_rw_ctxt_ctrl;
#define REG_RD_ADDR_dma_rw_ctxt_ctrl 40
#define REG_WR_ADDR_dma_rw_ctxt_ctrl 40
/* Register rw_ctxt_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 7;
unsigned int dis : 1;
unsigned int dummy2 : 24;
} reg_dma_rw_ctxt_stat;
#define REG_RD_ADDR_dma_rw_ctxt_stat 44
#define REG_WR_ADDR_dma_rw_ctxt_stat 44
/* Register rw_ctxt_md0, scope dma, type rw */
typedef struct {
unsigned int md0 : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0;
#define REG_RD_ADDR_dma_rw_ctxt_md0 48
#define REG_WR_ADDR_dma_rw_ctxt_md0 48
/* Register rw_ctxt_md0_s, scope dma, type rw */
typedef struct {
unsigned int md0_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_ctxt_md0_s;
#define REG_RD_ADDR_dma_rw_ctxt_md0_s 52
#define REG_WR_ADDR_dma_rw_ctxt_md0_s 52
/* Register rw_ctxt_md1, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1;
#define REG_RD_ADDR_dma_rw_ctxt_md1 56
#define REG_WR_ADDR_dma_rw_ctxt_md1 56
/* Register rw_ctxt_md1_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md1_s;
#define REG_RD_ADDR_dma_rw_ctxt_md1_s 60
#define REG_WR_ADDR_dma_rw_ctxt_md1_s 60
/* Register rw_ctxt_md2, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2;
#define REG_RD_ADDR_dma_rw_ctxt_md2 64
#define REG_WR_ADDR_dma_rw_ctxt_md2 64
/* Register rw_ctxt_md2_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md2_s;
#define REG_RD_ADDR_dma_rw_ctxt_md2_s 68
#define REG_WR_ADDR_dma_rw_ctxt_md2_s 68
/* Register rw_ctxt_md3, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3;
#define REG_RD_ADDR_dma_rw_ctxt_md3 72
#define REG_WR_ADDR_dma_rw_ctxt_md3 72
/* Register rw_ctxt_md3_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md3_s;
#define REG_RD_ADDR_dma_rw_ctxt_md3_s 76
#define REG_WR_ADDR_dma_rw_ctxt_md3_s 76
/* Register rw_ctxt_md4, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4;
#define REG_RD_ADDR_dma_rw_ctxt_md4 80
#define REG_WR_ADDR_dma_rw_ctxt_md4 80
/* Register rw_ctxt_md4_s, scope dma, type rw */
typedef unsigned int reg_dma_rw_ctxt_md4_s;
#define REG_RD_ADDR_dma_rw_ctxt_md4_s 84
#define REG_WR_ADDR_dma_rw_ctxt_md4_s 84
/* Register rw_saved_data, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data;
#define REG_RD_ADDR_dma_rw_saved_data 88
#define REG_WR_ADDR_dma_rw_saved_data 88
/* Register rw_saved_data_buf, scope dma, type rw */
typedef unsigned int reg_dma_rw_saved_data_buf;
#define REG_RD_ADDR_dma_rw_saved_data_buf 92
#define REG_WR_ADDR_dma_rw_saved_data_buf 92
/* Register rw_group, scope dma, type rw */
typedef unsigned int reg_dma_rw_group;
#define REG_RD_ADDR_dma_rw_group 96
#define REG_WR_ADDR_dma_rw_group 96
/* Register rw_group_next, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_next;
#define REG_RD_ADDR_dma_rw_group_next 100
#define REG_WR_ADDR_dma_rw_group_next 100
/* Register rw_group_ctrl, scope dma, type rw */
typedef struct {
unsigned int eol : 1;
unsigned int tol : 1;
unsigned int bol : 1;
unsigned int dummy1 : 1;
unsigned int intr : 1;
unsigned int dummy2 : 2;
unsigned int en : 1;
unsigned int dummy3 : 24;
} reg_dma_rw_group_ctrl;
#define REG_RD_ADDR_dma_rw_group_ctrl 104
#define REG_WR_ADDR_dma_rw_group_ctrl 104
/* Register rw_group_stat, scope dma, type rw */
typedef struct {
unsigned int dummy1 : 7;
unsigned int dis : 1;
unsigned int dummy2 : 24;
} reg_dma_rw_group_stat;
#define REG_RD_ADDR_dma_rw_group_stat 108
#define REG_WR_ADDR_dma_rw_group_stat 108
/* Register rw_group_md, scope dma, type rw */
typedef struct {
unsigned int md : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_group_md;
#define REG_RD_ADDR_dma_rw_group_md 112
#define REG_WR_ADDR_dma_rw_group_md 112
/* Register rw_group_md_s, scope dma, type rw */
typedef struct {
unsigned int md_s : 16;
unsigned int dummy1 : 16;
} reg_dma_rw_group_md_s;
#define REG_RD_ADDR_dma_rw_group_md_s 116
#define REG_WR_ADDR_dma_rw_group_md_s 116
/* Register rw_group_up, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_up;
#define REG_RD_ADDR_dma_rw_group_up 120
#define REG_WR_ADDR_dma_rw_group_up 120
/* Register rw_group_down, scope dma, type rw */
typedef unsigned int reg_dma_rw_group_down;
#define REG_RD_ADDR_dma_rw_group_down 124
#define REG_WR_ADDR_dma_rw_group_down 124
/* Register rw_cmd, scope dma, type rw */
typedef struct {
unsigned int cont_data : 1;
unsigned int dummy1 : 31;
} reg_dma_rw_cmd;
#define REG_RD_ADDR_dma_rw_cmd 128
#define REG_WR_ADDR_dma_rw_cmd 128
/* Register rw_cfg, scope dma, type rw */
typedef struct {
unsigned int en : 1;
unsigned int stop : 1;
unsigned int dummy1 : 30;
} reg_dma_rw_cfg;
#define REG_RD_ADDR_dma_rw_cfg 132
#define REG_WR_ADDR_dma_rw_cfg 132
/* Register rw_stat, scope dma, type rw */
typedef struct {
unsigned int mode : 5;
unsigned int list_state : 3;
unsigned int stream_cmd_src : 8;
unsigned int dummy1 : 8;
unsigned int buf : 8;
} reg_dma_rw_stat;
#define REG_RD_ADDR_dma_rw_stat 136
#define REG_WR_ADDR_dma_rw_stat 136
/* Register rw_intr_mask, scope dma, type rw */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_rw_intr_mask;
#define REG_RD_ADDR_dma_rw_intr_mask 140
#define REG_WR_ADDR_dma_rw_intr_mask 140
/* Register rw_ack_intr, scope dma, type rw */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_rw_ack_intr;
#define REG_RD_ADDR_dma_rw_ack_intr 144
#define REG_WR_ADDR_dma_rw_ack_intr 144
/* Register r_intr, scope dma, type r */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_r_intr;
#define REG_RD_ADDR_dma_r_intr 148
/* Register r_masked_intr, scope dma, type r */
typedef struct {
unsigned int group : 1;
unsigned int ctxt : 1;
unsigned int data : 1;
unsigned int in_eop : 1;
unsigned int stream_cmd : 1;
unsigned int dummy1 : 27;
} reg_dma_r_masked_intr;
#define REG_RD_ADDR_dma_r_masked_intr 152
/* Register rw_stream_cmd, scope dma, type rw */
typedef struct {
unsigned int cmd : 10;
unsigned int dummy1 : 6;
unsigned int n : 8;
unsigned int dummy2 : 7;
unsigned int busy : 1;
} reg_dma_rw_stream_cmd;
#define REG_RD_ADDR_dma_rw_stream_cmd 156
#define REG_WR_ADDR_dma_rw_stream_cmd 156
/* Constants */
enum {
regk_dma_ack_pkt = 0x00000100,
regk_dma_anytime = 0x00000001,
regk_dma_array = 0x00000008,
regk_dma_burst = 0x00000020,
regk_dma_client = 0x00000002,
regk_dma_copy_next = 0x00000010,
regk_dma_copy_up = 0x00000020,
regk_dma_data_at_eol = 0x00000001,
regk_dma_dis_c = 0x00000010,
regk_dma_dis_g = 0x00000020,
regk_dma_idle = 0x00000001,
regk_dma_intern = 0x00000004,
regk_dma_load_c = 0x00000200,
regk_dma_load_c_n = 0x00000280,
regk_dma_load_c_next = 0x00000240,
regk_dma_load_d = 0x00000140,
regk_dma_load_g = 0x00000300,
regk_dma_load_g_down = 0x000003c0,
regk_dma_load_g_next = 0x00000340,
regk_dma_load_g_up = 0x00000380,
regk_dma_next_en = 0x00000010,
regk_dma_next_pkt = 0x00000010,
regk_dma_no = 0x00000000,
regk_dma_only_at_wait = 0x00000000,
regk_dma_restore = 0x00000020,
regk_dma_rst = 0x00000001,
regk_dma_running = 0x00000004,
regk_dma_rw_cfg_default = 0x00000000,
regk_dma_rw_cmd_default = 0x00000000,
regk_dma_rw_intr_mask_default = 0x00000000,
regk_dma_rw_stat_default = 0x00000101,
regk_dma_rw_stream_cmd_default = 0x00000000,
regk_dma_save_down = 0x00000020,
regk_dma_save_up = 0x00000020,
regk_dma_set_reg = 0x00000050,
regk_dma_set_w_size1 = 0x00000190,
regk_dma_set_w_size2 = 0x000001a0,
regk_dma_set_w_size4 = 0x000001c0,
regk_dma_stopped = 0x00000002,
regk_dma_store_c = 0x00000002,
regk_dma_store_descr = 0x00000000,
regk_dma_store_g = 0x00000004,
regk_dma_store_md = 0x00000001,
regk_dma_sw = 0x00000008,
regk_dma_update_down = 0x00000020,
regk_dma_yes = 0x00000001
};
#endif /* __dma_defs_h */
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