Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 | /*
* Meta performance counter support.
* Copyright (C) 2012 Imagination Technologies Ltd
*
* This code is based on the sh pmu code:
* Copyright (C) 2009 Paul Mundt
*
* and on the arm pmu code:
* Copyright (C) 2009 picoChip Designs, Ltd., James Iles
* Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/atomic.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/irqchip/metag.h>
#include <linux/perf_event.h>
#include <linux/slab.h>
#include <asm/core_reg.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/processor.h>
#include "perf_event.h"
static int _hw_perf_event_init(struct perf_event *);
static void _hw_perf_event_destroy(struct perf_event *);
/* Determines which core type we are */
static struct metag_pmu *metag_pmu __read_mostly;
/* Processor specific data */
static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
/* PMU admin */
const char *perf_pmu_name(void)
{
if (!metag_pmu)
return NULL;
return metag_pmu->name;
}
EXPORT_SYMBOL_GPL(perf_pmu_name);
int perf_num_counters(void)
{
if (metag_pmu)
return metag_pmu->max_events;
return 0;
}
EXPORT_SYMBOL_GPL(perf_num_counters);
static inline int metag_pmu_initialised(void)
{
return !!metag_pmu;
}
static void release_pmu_hardware(void)
{
int irq;
unsigned int version = (metag_pmu->version &
(METAC_ID_MINOR_BITS | METAC_ID_REV_BITS)) >>
METAC_ID_REV_S;
/* Early cores don't have overflow interrupts */
if (version < 0x0104)
return;
irq = internal_irq_map(17);
if (irq >= 0)
free_irq(irq, (void *)1);
irq = internal_irq_map(16);
if (irq >= 0)
free_irq(irq, (void *)0);
}
static int reserve_pmu_hardware(void)
{
int err = 0, irq[2];
unsigned int version = (metag_pmu->version &
(METAC_ID_MINOR_BITS | METAC_ID_REV_BITS)) >>
METAC_ID_REV_S;
/* Early cores don't have overflow interrupts */
if (version < 0x0104)
goto out;
/*
* Bit 16 on HWSTATMETA is the interrupt for performance counter 0;
* similarly, 17 is the interrupt for performance counter 1.
* We can't (yet) interrupt on the cycle counter, because it's a
* register, however it holds a 32-bit value as opposed to 24-bit.
*/
irq[0] = internal_irq_map(16);
if (irq[0] < 0) {
pr_err("unable to map internal IRQ %d\n", 16);
goto out;
}
err = request_irq(irq[0], metag_pmu->handle_irq, IRQF_NOBALANCING,
"metagpmu0", (void *)0);
if (err) {
pr_err("unable to request IRQ%d for metag PMU counters\n",
irq[0]);
goto out;
}
irq[1] = internal_irq_map(17);
if (irq[1] < 0) {
pr_err("unable to map internal IRQ %d\n", 17);
goto out_irq1;
}
err = request_irq(irq[1], metag_pmu->handle_irq, IRQF_NOBALANCING,
"metagpmu1", (void *)1);
if (err) {
pr_err("unable to request IRQ%d for metag PMU counters\n",
irq[1]);
goto out_irq1;
}
return 0;
out_irq1:
free_irq(irq[0], (void *)0);
out:
return err;
}
/* PMU operations */
static void metag_pmu_enable(struct pmu *pmu)
{
}
static void metag_pmu_disable(struct pmu *pmu)
{
}
static int metag_pmu_event_init(struct perf_event *event)
{
int err = 0;
atomic_t *active_events = &metag_pmu->active_events;
if (!metag_pmu_initialised()) {
err = -ENODEV;
goto out;
}
if (has_branch_stack(event))
return -EOPNOTSUPP;
event->destroy = _hw_perf_event_destroy;
if (!atomic_inc_not_zero(active_events)) {
mutex_lock(&metag_pmu->reserve_mutex);
if (atomic_read(active_events) == 0)
err = reserve_pmu_hardware();
if (!err)
atomic_inc(active_events);
mutex_unlock(&metag_pmu->reserve_mutex);
}
/* Hardware and caches counters */
switch (event->attr.type) {
case PERF_TYPE_HARDWARE:
case PERF_TYPE_HW_CACHE:
case PERF_TYPE_RAW:
err = _hw_perf_event_init(event);
break;
default:
return -ENOENT;
}
if (err)
event->destroy(event);
out:
return err;
}
void metag_pmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc, int idx)
{
u64 prev_raw_count, new_raw_count;
s64 delta;
/*
* If this counter is chained, it may be that the previous counter
* value has been changed beneath us.
*
* To get around this, we read and exchange the new raw count, then
* add the delta (new - prev) to the generic counter atomically.
*
* Without interrupts, this is the simplest approach.
*/
again:
prev_raw_count = local64_read(&hwc->prev_count);
new_raw_count = metag_pmu->read(idx);
if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
new_raw_count) != prev_raw_count)
goto again;
/*
* Calculate the delta and add it to the counter.
*/
delta = (new_raw_count - prev_raw_count) & MAX_PERIOD;
local64_add(delta, &event->count);
local64_sub(delta, &hwc->period_left);
}
int metag_pmu_event_set_period(struct perf_event *event,
struct hw_perf_event *hwc, int idx)
{
s64 left = local64_read(&hwc->period_left);
s64 period = hwc->sample_period;
int ret = 0;
/* The period may have been changed */
if (unlikely(period != hwc->last_period))
left += period - hwc->last_period;
if (unlikely(left <= -period)) {
left = period;
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
if (unlikely(left <= 0)) {
left += period;
local64_set(&hwc->period_left, left);
hwc->last_period = period;
ret = 1;
}
if (left > (s64)metag_pmu->max_period)
left = metag_pmu->max_period;
if (metag_pmu->write) {
local64_set(&hwc->prev_count, -(s32)left);
metag_pmu->write(idx, -left & MAX_PERIOD);
}
perf_event_update_userpage(event);
return ret;
}
static void metag_pmu_start(struct perf_event *event, int flags)
{
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
struct hw_perf_event *hwc = &event->hw;
int idx = hwc->idx;
if (WARN_ON_ONCE(idx == -1))
return;
/*
* We always have to reprogram the period, so ignore PERF_EF_RELOAD.
*/
if (flags & PERF_EF_RELOAD)
WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
hwc->state = 0;
/*
* Reset the period.
* Some counters can't be stopped (i.e. are core global), so when the
* counter was 'stopped' we merely disabled the IRQ. If we don't reset
* the period, then we'll either: a) get an overflow too soon;
* or b) too late if the overflow happened since disabling.
* Obviously, this has little bearing on cores without the overflow
* interrupt, as the performance counter resets to zero on write
* anyway.
*/
if (metag_pmu->max_period)
metag_pmu_event_set_period(event, hwc, hwc->idx);
cpuc->events[idx] = event;
metag_pmu->enable(hwc, idx);
}
static void metag_pmu_stop(struct perf_event *event, int flags)
{
struct hw_perf_event *hwc = &event->hw;
/*
* We should always update the counter on stop; see comment above
* why.
*/
if (!(hwc->state & PERF_HES_STOPPED)) {
metag_pmu_event_update(event, hwc, hwc->idx);
metag_pmu->disable(hwc, hwc->idx);
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
}
}
static int metag_pmu_add(struct perf_event *event, int flags)
{
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
struct hw_perf_event *hwc = &event->hw;
int idx = 0, ret = 0;
perf_pmu_disable(event->pmu);
/* check whether we're counting instructions */
if (hwc->config == 0x100) {
if (__test_and_set_bit(METAG_INST_COUNTER,
cpuc->used_mask)) {
ret = -EAGAIN;
goto out;
}
idx = METAG_INST_COUNTER;
} else {
/* Check whether we have a spare counter */
idx = find_first_zero_bit(cpuc->used_mask,
atomic_read(&metag_pmu->active_events));
if (idx >= METAG_INST_COUNTER) {
ret = -EAGAIN;
goto out;
}
__set_bit(idx, cpuc->used_mask);
}
hwc->idx = idx;
/* Make sure the counter is disabled */
metag_pmu->disable(hwc, idx);
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
if (flags & PERF_EF_START)
metag_pmu_start(event, PERF_EF_RELOAD);
perf_event_update_userpage(event);
out:
perf_pmu_enable(event->pmu);
return ret;
}
static void metag_pmu_del(struct perf_event *event, int flags)
{
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
struct hw_perf_event *hwc = &event->hw;
int idx = hwc->idx;
WARN_ON(idx < 0);
metag_pmu_stop(event, PERF_EF_UPDATE);
cpuc->events[idx] = NULL;
__clear_bit(idx, cpuc->used_mask);
perf_event_update_userpage(event);
}
static void metag_pmu_read(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
/* Don't read disabled counters! */
if (hwc->idx < 0)
return;
metag_pmu_event_update(event, hwc, hwc->idx);
}
static struct pmu pmu = {
.pmu_enable = metag_pmu_enable,
.pmu_disable = metag_pmu_disable,
.event_init = metag_pmu_event_init,
.add = metag_pmu_add,
.del = metag_pmu_del,
.start = metag_pmu_start,
.stop = metag_pmu_stop,
.read = metag_pmu_read,
};
/* Core counter specific functions */
static const int metag_general_events[] = {
[PERF_COUNT_HW_CPU_CYCLES] = 0x03,
[PERF_COUNT_HW_INSTRUCTIONS] = 0x100,
[PERF_COUNT_HW_CACHE_REFERENCES] = -1,
[PERF_COUNT_HW_CACHE_MISSES] = -1,
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = -1,
[PERF_COUNT_HW_BRANCH_MISSES] = -1,
[PERF_COUNT_HW_BUS_CYCLES] = -1,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = -1,
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = -1,
[PERF_COUNT_HW_REF_CPU_CYCLES] = -1,
};
static const int metag_pmu_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[C(L1D)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x08,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(L1I)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0x09,
[C(RESULT_MISS)] = 0x0a,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(LL)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(DTLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0xd0,
[C(RESULT_MISS)] = 0xd2,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = 0xd4,
[C(RESULT_MISS)] = 0xd5,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(ITLB)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = 0xd1,
[C(RESULT_MISS)] = 0xd3,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(BPU)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
[C(NODE)] = {
[C(OP_READ)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_WRITE)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
[C(OP_PREFETCH)] = {
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
};
static void _hw_perf_event_destroy(struct perf_event *event)
{
atomic_t *active_events = &metag_pmu->active_events;
struct mutex *pmu_mutex = &metag_pmu->reserve_mutex;
if (atomic_dec_and_mutex_lock(active_events, pmu_mutex)) {
release_pmu_hardware();
mutex_unlock(pmu_mutex);
}
}
static int _hw_perf_cache_event(int config, int *evp)
{
unsigned long type, op, result;
int ev;
if (!metag_pmu->cache_events)
return -EINVAL;
/* Unpack config */
type = config & 0xff;
op = (config >> 8) & 0xff;
result = (config >> 16) & 0xff;
if (type >= PERF_COUNT_HW_CACHE_MAX ||
op >= PERF_COUNT_HW_CACHE_OP_MAX ||
result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
return -EINVAL;
ev = (*metag_pmu->cache_events)[type][op][result];
if (ev == 0)
return -EOPNOTSUPP;
if (ev == -1)
return -EINVAL;
*evp = ev;
return 0;
}
static int _hw_perf_event_init(struct perf_event *event)
{
struct perf_event_attr *attr = &event->attr;
struct hw_perf_event *hwc = &event->hw;
int mapping = 0, err;
switch (attr->type) {
case PERF_TYPE_HARDWARE:
if (attr->config >= PERF_COUNT_HW_MAX)
return -EINVAL;
mapping = metag_pmu->event_map(attr->config);
break;
case PERF_TYPE_HW_CACHE:
err = _hw_perf_cache_event(attr->config, &mapping);
if (err)
return err;
break;
case PERF_TYPE_RAW:
mapping = attr->config;
break;
}
/* Return early if the event is unsupported */
if (mapping == -1)
return -EINVAL;
/*
* Early cores have "limited" counters - they have no overflow
* interrupts - and so are unable to do sampling without extra work
* and timer assistance.
*/
if (metag_pmu->max_period == 0) {
if (hwc->sample_period)
return -EINVAL;
}
/*
* Don't assign an index until the event is placed into the hardware.
* -1 signifies that we're still deciding where to put it. On SMP
* systems each core has its own set of counters, so we can't do any
* constraint checking yet.
*/
hwc->idx = -1;
/* Store the event encoding */
hwc->config |= (unsigned long)mapping;
/*
* For non-sampling runs, limit the sample_period to half of the
* counter width. This way, the new counter value should be less
* likely to overtake the previous one (unless there are IRQ latency
* issues...)
*/
if (metag_pmu->max_period) {
if (!hwc->sample_period) {
hwc->sample_period = metag_pmu->max_period >> 1;
hwc->last_period = hwc->sample_period;
local64_set(&hwc->period_left, hwc->sample_period);
}
}
return 0;
}
static void metag_pmu_enable_counter(struct hw_perf_event *event, int idx)
{
struct cpu_hw_events *events = &__get_cpu_var(cpu_hw_events);
unsigned int config = event->config;
unsigned int tmp = config & 0xf0;
unsigned long flags;
raw_spin_lock_irqsave(&events->pmu_lock, flags);
/*
* Check if we're enabling the instruction counter (index of
* MAX_HWEVENTS - 1)
*/
if (METAG_INST_COUNTER == idx) {
WARN_ONCE((config != 0x100),
"invalid configuration (%d) for counter (%d)\n",
config, idx);
local64_set(&event->prev_count, __core_reg_get(TXTACTCYC));
goto unlock;
}
/* Check for a core internal or performance channel event. */
if (tmp) {
void *perf_addr;
/*
* Anything other than a cycle count will write the low-
* nibble to the correct counter register.
*/
switch (tmp) {
case 0xd0:
perf_addr = (void *)PERF_ICORE(idx);
break;
case 0xf0:
perf_addr = (void *)PERF_CHAN(idx);
break;
default:
perf_addr = NULL;
break;
}
if (perf_addr)
metag_out32((config & 0x0f), perf_addr);
/*
* Now we use the high nibble as the performance event to
* to count.
*/
config = tmp >> 4;
}
tmp = ((config & 0xf) << 28) |
((1 << 24) << hard_processor_id());
if (metag_pmu->max_period)
/*
* Cores supporting overflow interrupts may have had the counter
* set to a specific value that needs preserving.
*/
tmp |= metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
else
/*
* Older cores reset the counter on write, so prev_count needs
* resetting too so we can calculate a correct delta.
*/
local64_set(&event->prev_count, 0);
metag_out32(tmp, PERF_COUNT(idx));
unlock:
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
static void metag_pmu_disable_counter(struct hw_perf_event *event, int idx)
{
struct cpu_hw_events *events = &__get_cpu_var(cpu_hw_events);
unsigned int tmp = 0;
unsigned long flags;
/*
* The cycle counter can't be disabled per se, as it's a hardware
* thread register which is always counting. We merely return if this
* is the counter we're attempting to disable.
*/
if (METAG_INST_COUNTER == idx)
return;
/*
* The counter value _should_ have been read prior to disabling,
* as if we're running on an early core then the value gets reset to
* 0, and any read after that would be useless. On the newer cores,
* however, it's better to read-modify-update this for purposes of
* the overflow interrupt.
* Here we remove the thread id AND the event nibble (there are at
* least two events that count events that are core global and ignore
* the thread id mask). This only works because we don't mix thread
* performance counts, and event 0x00 requires a thread id mask!
*/
raw_spin_lock_irqsave(&events->pmu_lock, flags);
tmp = metag_in32(PERF_COUNT(idx));
tmp &= 0x00ffffff;
metag_out32(tmp, PERF_COUNT(idx));
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
static u64 metag_pmu_read_counter(int idx)
{
u32 tmp = 0;
if (METAG_INST_COUNTER == idx) {
tmp = __core_reg_get(TXTACTCYC);
goto out;
}
tmp = metag_in32(PERF_COUNT(idx)) & 0x00ffffff;
out:
return tmp;
}
static void metag_pmu_write_counter(int idx, u32 val)
{
struct cpu_hw_events *events = &__get_cpu_var(cpu_hw_events);
u32 tmp = 0;
unsigned long flags;
/*
* This _shouldn't_ happen, but if it does, then we can just
* ignore the write, as the register is read-only and clear-on-write.
*/
if (METAG_INST_COUNTER == idx)
return;
/*
* We'll keep the thread mask and event id, and just update the
* counter itself. Also , we should bound the value to 24-bits.
*/
raw_spin_lock_irqsave(&events->pmu_lock, flags);
val &= 0x00ffffff;
tmp = metag_in32(PERF_COUNT(idx)) & 0xff000000;
val |= tmp;
metag_out32(val, PERF_COUNT(idx));
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
}
static int metag_pmu_event_map(int idx)
{
return metag_general_events[idx];
}
static irqreturn_t metag_pmu_counter_overflow(int irq, void *dev)
{
int idx = (int)dev;
struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
struct perf_event *event = cpuhw->events[idx];
struct hw_perf_event *hwc = &event->hw;
struct pt_regs *regs = get_irq_regs();
struct perf_sample_data sampledata;
unsigned long flags;
u32 counter = 0;
/*
* We need to stop the core temporarily from generating another
* interrupt while we disable this counter. However, we don't want
* to flag the counter as free
*/
__global_lock2(flags);
counter = metag_in32(PERF_COUNT(idx));
metag_out32((counter & 0x00ffffff), PERF_COUNT(idx));
__global_unlock2(flags);
/* Update the counts and reset the sample period */
metag_pmu_event_update(event, hwc, idx);
perf_sample_data_init(&sampledata, 0, hwc->last_period);
metag_pmu_event_set_period(event, hwc, idx);
/*
* Enable the counter again once core overflow processing has
* completed. Note the counter value may have been modified while it was
* inactive to set it up ready for the next interrupt.
*/
if (!perf_event_overflow(event, &sampledata, regs)) {
__global_lock2(flags);
counter = (counter & 0xff000000) |
(metag_in32(PERF_COUNT(idx)) & 0x00ffffff);
metag_out32(counter, PERF_COUNT(idx));
__global_unlock2(flags);
}
return IRQ_HANDLED;
}
static struct metag_pmu _metag_pmu = {
.handle_irq = metag_pmu_counter_overflow,
.enable = metag_pmu_enable_counter,
.disable = metag_pmu_disable_counter,
.read = metag_pmu_read_counter,
.write = metag_pmu_write_counter,
.event_map = metag_pmu_event_map,
.cache_events = &metag_pmu_cache_events,
.max_period = MAX_PERIOD,
.max_events = MAX_HWEVENTS,
};
/* PMU CPU hotplug notifier */
static int metag_pmu_cpu_notify(struct notifier_block *b, unsigned long action,
void *hcpu)
{
unsigned int cpu = (unsigned int)hcpu;
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
return NOTIFY_DONE;
memset(cpuc, 0, sizeof(struct cpu_hw_events));
raw_spin_lock_init(&cpuc->pmu_lock);
return NOTIFY_OK;
}
static struct notifier_block metag_pmu_notifier = {
.notifier_call = metag_pmu_cpu_notify,
};
/* PMU Initialisation */
static int __init init_hw_perf_events(void)
{
int ret = 0, cpu;
u32 version = *(u32 *)METAC_ID;
int major = (version & METAC_ID_MAJOR_BITS) >> METAC_ID_MAJOR_S;
int min_rev = (version & (METAC_ID_MINOR_BITS | METAC_ID_REV_BITS))
>> METAC_ID_REV_S;
/* Not a Meta 2 core, then not supported */
if (0x02 > major) {
pr_info("no hardware counter support available\n");
goto out;
} else if (0x02 == major) {
metag_pmu = &_metag_pmu;
if (min_rev < 0x0104) {
/*
* A core without overflow interrupts, and clear-on-
* write counters.
*/
metag_pmu->handle_irq = NULL;
metag_pmu->write = NULL;
metag_pmu->max_period = 0;
}
metag_pmu->name = "meta2";
metag_pmu->version = version;
metag_pmu->pmu = pmu;
}
pr_info("enabled with %s PMU driver, %d counters available\n",
metag_pmu->name, metag_pmu->max_events);
/* Initialise the active events and reservation mutex */
atomic_set(&metag_pmu->active_events, 0);
mutex_init(&metag_pmu->reserve_mutex);
/* Clear the counters */
metag_out32(0, PERF_COUNT(0));
metag_out32(0, PERF_COUNT(1));
for_each_possible_cpu(cpu) {
struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
memset(cpuc, 0, sizeof(struct cpu_hw_events));
raw_spin_lock_init(&cpuc->pmu_lock);
}
register_cpu_notifier(&metag_pmu_notifier);
ret = perf_pmu_register(&pmu, metag_pmu->name, PERF_TYPE_RAW);
out:
return ret;
}
early_initcall(init_hw_perf_events);
|