Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 | /*
* Here is where the ball gets rolling as far as the kernel is concerned.
* When control is transferred to _start, the bootload has already
* loaded us to the correct address. All that's left to do here is
* to set up the kernel's global pointer and jump to the kernel
* entry point.
*
* Copyright (C) 1998-2000 Hewlett-Packard Co
* Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
* Copyright (C) 1999 VA Linux Systems
* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
* Copyright (C) 1999 Intel Corp.
* Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
* Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
*/
#include <linux/config.h>
#include <asm/asmmacro.h>
#include <asm/fpu.h>
#include <asm/pal.h>
#include <asm/offsets.h>
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/system.h>
.psr abi64
.psr lsb
.lsb
.section __special_page_section,"ax"
.global empty_zero_page
empty_zero_page:
.skip PAGE_SIZE
.global swapper_pg_dir
swapper_pg_dir:
.skip PAGE_SIZE
.global empty_bad_page
empty_bad_page:
.skip PAGE_SIZE
.global empty_bad_pte_table
empty_bad_pte_table:
.skip PAGE_SIZE
.global empty_bad_pmd_table
empty_bad_pmd_table:
.skip PAGE_SIZE
.rodata
halt_msg:
stringz "Halting kernel\n"
.text
GLOBAL_ENTRY(_start)
UNW(.prologue)
UNW(.save rp, r4) // terminate unwind chain with a NULL rp
UNW(mov r4=r0)
UNW(.body)
// set IVT entry point---can't access I/O ports without it
movl r3=ia64_ivt
;;
mov cr.iva=r3
movl r2=FPSR_DEFAULT
;;
srlz.i
movl gp=__gp
mov ar.fpsr=r2
;;
#ifdef CONFIG_IA64_EARLY_PRINTK
mov r2=6
mov r3=(8<<8) | (28<<2)
;;
mov rr[r2]=r3
;;
srlz.i
;;
#endif
#define isAP p2 // are we booting an Application Processor (not the BSP)?
// Find the init_task for the currently booting CPU. At poweron, and in
// UP mode, cpu_now_booting is 0
movl r3=cpu_now_booting
;;
ld4 r3=[r3]
movl r2=init_tasks
;;
shladd r2=r3,3,r2
;;
ld8 r2=[r2]
cmp4.ne isAP,p0=r3,r0 // p9 == true if this is an application processor (ap)
;; // RAW on r2
extr r3=r2,0,61 // r3 == phys addr of task struct
;;
// load the "current" pointer (r13) and ar.k6 with the current task
mov r13=r2
mov ar.k6=r3 // Physical address
;;
/*
* Reserve space at the top of the stack for "struct pt_regs". Kernel threads
* don't store interesting values in that structure, but the space still needs
* to be there because time-critical stuff such as the context switching can
* be implemented more efficiently (for example, __switch_to()
* always sets the psr.dfh bit of the task it is switching to).
*/
addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2
addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
mov ar.rsc=r0 // place RSE in enforced lazy mode
;;
mov ar.bspstore=r2 // establish the new RSE stack
;;
loadrs // load zero bytes from the register stack
;;
mov ar.rsc=0x3 // place RSE in eager mode
;;
#ifdef CONFIG_IA64_EARLY_PRINTK
.rodata
alive_msg:
stringz "I'm alive and well\n"
.previous
alloc r2=ar.pfs,0,0,2,0
movl out0=alive_msg
;;
br.call.sptk.few rp=early_printk
1: // force new bundle
#endif /* CONFIG_IA64_EARLY_PRINTK */
alloc r2=ar.pfs,8,0,2,0
;;
#ifdef CONFIG_SMP
(isAP) br.call.sptk.few rp=smp_callin
.ret0:
(isAP) br.cond.sptk.few self
#endif
#undef isAP
// This is executed by the bootstrap processor (bsp) only:
#ifdef CONFIG_IA64_FW_EMU
// initialize PAL & SAL emulator:
br.call.sptk.few rp=sys_fw_init
.ret1:
#endif
br.call.sptk.few rp=start_kernel
.ret2: addl r2=@ltoff(halt_msg),gp
;;
ld8 out0=[r2]
br.call.sptk.few b0=console_print
self: br.sptk.few self // endless loop
END(_start)
GLOBAL_ENTRY(ia64_save_debug_regs)
alloc r16=ar.pfs,1,0,0,0
mov r20=ar.lc // preserve ar.lc
mov ar.lc=IA64_NUM_DBG_REGS-1
mov r18=0
add r19=IA64_NUM_DBG_REGS*8,in0
;;
1: mov r16=dbr[r18]
mov r17=ibr[r18]
add r18=1,r18
;;
st8.nta [in0]=r16,8
st8.nta [r19]=r17,8
br.cloop.sptk.few 1b
;;
mov ar.lc=r20 // restore ar.lc
br.ret.sptk.few rp
END(ia64_save_debug_regs)
GLOBAL_ENTRY(ia64_load_debug_regs)
alloc r16=ar.pfs,1,0,0,0
lfetch.nta [in0]
mov r20=ar.lc // preserve ar.lc
add r19=IA64_NUM_DBG_REGS*8,in0
mov ar.lc=IA64_NUM_DBG_REGS-1
mov r18=-1
;;
1: ld8.nta r16=[in0],8
ld8.nta r17=[r19],8
add r18=1,r18
;;
mov dbr[r18]=r16
mov ibr[r18]=r17
br.cloop.sptk.few 1b
;;
mov ar.lc=r20 // restore ar.lc
br.ret.sptk.few rp
END(ia64_load_debug_regs)
GLOBAL_ENTRY(__ia64_save_fpu)
alloc r2=ar.pfs,1,0,0,0
adds r3=16,in0
;;
stf.spill.nta [in0]=f32,32
stf.spill.nta [ r3]=f33,32
;;
stf.spill.nta [in0]=f34,32
stf.spill.nta [ r3]=f35,32
;;
stf.spill.nta [in0]=f36,32
stf.spill.nta [ r3]=f37,32
;;
stf.spill.nta [in0]=f38,32
stf.spill.nta [ r3]=f39,32
;;
stf.spill.nta [in0]=f40,32
stf.spill.nta [ r3]=f41,32
;;
stf.spill.nta [in0]=f42,32
stf.spill.nta [ r3]=f43,32
;;
stf.spill.nta [in0]=f44,32
stf.spill.nta [ r3]=f45,32
;;
stf.spill.nta [in0]=f46,32
stf.spill.nta [ r3]=f47,32
;;
stf.spill.nta [in0]=f48,32
stf.spill.nta [ r3]=f49,32
;;
stf.spill.nta [in0]=f50,32
stf.spill.nta [ r3]=f51,32
;;
stf.spill.nta [in0]=f52,32
stf.spill.nta [ r3]=f53,32
;;
stf.spill.nta [in0]=f54,32
stf.spill.nta [ r3]=f55,32
;;
stf.spill.nta [in0]=f56,32
stf.spill.nta [ r3]=f57,32
;;
stf.spill.nta [in0]=f58,32
stf.spill.nta [ r3]=f59,32
;;
stf.spill.nta [in0]=f60,32
stf.spill.nta [ r3]=f61,32
;;
stf.spill.nta [in0]=f62,32
stf.spill.nta [ r3]=f63,32
;;
stf.spill.nta [in0]=f64,32
stf.spill.nta [ r3]=f65,32
;;
stf.spill.nta [in0]=f66,32
stf.spill.nta [ r3]=f67,32
;;
stf.spill.nta [in0]=f68,32
stf.spill.nta [ r3]=f69,32
;;
stf.spill.nta [in0]=f70,32
stf.spill.nta [ r3]=f71,32
;;
stf.spill.nta [in0]=f72,32
stf.spill.nta [ r3]=f73,32
;;
stf.spill.nta [in0]=f74,32
stf.spill.nta [ r3]=f75,32
;;
stf.spill.nta [in0]=f76,32
stf.spill.nta [ r3]=f77,32
;;
stf.spill.nta [in0]=f78,32
stf.spill.nta [ r3]=f79,32
;;
stf.spill.nta [in0]=f80,32
stf.spill.nta [ r3]=f81,32
;;
stf.spill.nta [in0]=f82,32
stf.spill.nta [ r3]=f83,32
;;
stf.spill.nta [in0]=f84,32
stf.spill.nta [ r3]=f85,32
;;
stf.spill.nta [in0]=f86,32
stf.spill.nta [ r3]=f87,32
;;
stf.spill.nta [in0]=f88,32
stf.spill.nta [ r3]=f89,32
;;
stf.spill.nta [in0]=f90,32
stf.spill.nta [ r3]=f91,32
;;
stf.spill.nta [in0]=f92,32
stf.spill.nta [ r3]=f93,32
;;
stf.spill.nta [in0]=f94,32
stf.spill.nta [ r3]=f95,32
;;
stf.spill.nta [in0]=f96,32
stf.spill.nta [ r3]=f97,32
;;
stf.spill.nta [in0]=f98,32
stf.spill.nta [ r3]=f99,32
;;
stf.spill.nta [in0]=f100,32
stf.spill.nta [ r3]=f101,32
;;
stf.spill.nta [in0]=f102,32
stf.spill.nta [ r3]=f103,32
;;
stf.spill.nta [in0]=f104,32
stf.spill.nta [ r3]=f105,32
;;
stf.spill.nta [in0]=f106,32
stf.spill.nta [ r3]=f107,32
;;
stf.spill.nta [in0]=f108,32
stf.spill.nta [ r3]=f109,32
;;
stf.spill.nta [in0]=f110,32
stf.spill.nta [ r3]=f111,32
;;
stf.spill.nta [in0]=f112,32
stf.spill.nta [ r3]=f113,32
;;
stf.spill.nta [in0]=f114,32
stf.spill.nta [ r3]=f115,32
;;
stf.spill.nta [in0]=f116,32
stf.spill.nta [ r3]=f117,32
;;
stf.spill.nta [in0]=f118,32
stf.spill.nta [ r3]=f119,32
;;
stf.spill.nta [in0]=f120,32
stf.spill.nta [ r3]=f121,32
;;
stf.spill.nta [in0]=f122,32
stf.spill.nta [ r3]=f123,32
;;
stf.spill.nta [in0]=f124,32
stf.spill.nta [ r3]=f125,32
;;
stf.spill.nta [in0]=f126,32
stf.spill.nta [ r3]=f127,32
br.ret.sptk.few rp
END(__ia64_save_fpu)
GLOBAL_ENTRY(__ia64_load_fpu)
alloc r2=ar.pfs,1,0,0,0
adds r3=16,in0
;;
ldf.fill.nta f32=[in0],32
ldf.fill.nta f33=[ r3],32
;;
ldf.fill.nta f34=[in0],32
ldf.fill.nta f35=[ r3],32
;;
ldf.fill.nta f36=[in0],32
ldf.fill.nta f37=[ r3],32
;;
ldf.fill.nta f38=[in0],32
ldf.fill.nta f39=[ r3],32
;;
ldf.fill.nta f40=[in0],32
ldf.fill.nta f41=[ r3],32
;;
ldf.fill.nta f42=[in0],32
ldf.fill.nta f43=[ r3],32
;;
ldf.fill.nta f44=[in0],32
ldf.fill.nta f45=[ r3],32
;;
ldf.fill.nta f46=[in0],32
ldf.fill.nta f47=[ r3],32
;;
ldf.fill.nta f48=[in0],32
ldf.fill.nta f49=[ r3],32
;;
ldf.fill.nta f50=[in0],32
ldf.fill.nta f51=[ r3],32
;;
ldf.fill.nta f52=[in0],32
ldf.fill.nta f53=[ r3],32
;;
ldf.fill.nta f54=[in0],32
ldf.fill.nta f55=[ r3],32
;;
ldf.fill.nta f56=[in0],32
ldf.fill.nta f57=[ r3],32
;;
ldf.fill.nta f58=[in0],32
ldf.fill.nta f59=[ r3],32
;;
ldf.fill.nta f60=[in0],32
ldf.fill.nta f61=[ r3],32
;;
ldf.fill.nta f62=[in0],32
ldf.fill.nta f63=[ r3],32
;;
ldf.fill.nta f64=[in0],32
ldf.fill.nta f65=[ r3],32
;;
ldf.fill.nta f66=[in0],32
ldf.fill.nta f67=[ r3],32
;;
ldf.fill.nta f68=[in0],32
ldf.fill.nta f69=[ r3],32
;;
ldf.fill.nta f70=[in0],32
ldf.fill.nta f71=[ r3],32
;;
ldf.fill.nta f72=[in0],32
ldf.fill.nta f73=[ r3],32
;;
ldf.fill.nta f74=[in0],32
ldf.fill.nta f75=[ r3],32
;;
ldf.fill.nta f76=[in0],32
ldf.fill.nta f77=[ r3],32
;;
ldf.fill.nta f78=[in0],32
ldf.fill.nta f79=[ r3],32
;;
ldf.fill.nta f80=[in0],32
ldf.fill.nta f81=[ r3],32
;;
ldf.fill.nta f82=[in0],32
ldf.fill.nta f83=[ r3],32
;;
ldf.fill.nta f84=[in0],32
ldf.fill.nta f85=[ r3],32
;;
ldf.fill.nta f86=[in0],32
ldf.fill.nta f87=[ r3],32
;;
ldf.fill.nta f88=[in0],32
ldf.fill.nta f89=[ r3],32
;;
ldf.fill.nta f90=[in0],32
ldf.fill.nta f91=[ r3],32
;;
ldf.fill.nta f92=[in0],32
ldf.fill.nta f93=[ r3],32
;;
ldf.fill.nta f94=[in0],32
ldf.fill.nta f95=[ r3],32
;;
ldf.fill.nta f96=[in0],32
ldf.fill.nta f97=[ r3],32
;;
ldf.fill.nta f98=[in0],32
ldf.fill.nta f99=[ r3],32
;;
ldf.fill.nta f100=[in0],32
ldf.fill.nta f101=[ r3],32
;;
ldf.fill.nta f102=[in0],32
ldf.fill.nta f103=[ r3],32
;;
ldf.fill.nta f104=[in0],32
ldf.fill.nta f105=[ r3],32
;;
ldf.fill.nta f106=[in0],32
ldf.fill.nta f107=[ r3],32
;;
ldf.fill.nta f108=[in0],32
ldf.fill.nta f109=[ r3],32
;;
ldf.fill.nta f110=[in0],32
ldf.fill.nta f111=[ r3],32
;;
ldf.fill.nta f112=[in0],32
ldf.fill.nta f113=[ r3],32
;;
ldf.fill.nta f114=[in0],32
ldf.fill.nta f115=[ r3],32
;;
ldf.fill.nta f116=[in0],32
ldf.fill.nta f117=[ r3],32
;;
ldf.fill.nta f118=[in0],32
ldf.fill.nta f119=[ r3],32
;;
ldf.fill.nta f120=[in0],32
ldf.fill.nta f121=[ r3],32
;;
ldf.fill.nta f122=[in0],32
ldf.fill.nta f123=[ r3],32
;;
ldf.fill.nta f124=[in0],32
ldf.fill.nta f125=[ r3],32
;;
ldf.fill.nta f126=[in0],32
ldf.fill.nta f127=[ r3],32
br.ret.sptk.few rp
END(__ia64_load_fpu)
GLOBAL_ENTRY(__ia64_init_fpu)
alloc r2=ar.pfs,0,0,0,0
stf.spill [sp]=f0
mov f32=f0
;;
ldf.fill f33=[sp]
ldf.fill f34=[sp]
mov f35=f0
;;
ldf.fill f36=[sp]
ldf.fill f37=[sp]
mov f38=f0
;;
ldf.fill f39=[sp]
ldf.fill f40=[sp]
mov f41=f0
;;
ldf.fill f42=[sp]
ldf.fill f43=[sp]
mov f44=f0
;;
ldf.fill f45=[sp]
ldf.fill f46=[sp]
mov f47=f0
;;
ldf.fill f48=[sp]
ldf.fill f49=[sp]
mov f50=f0
;;
ldf.fill f51=[sp]
ldf.fill f52=[sp]
mov f53=f0
;;
ldf.fill f54=[sp]
ldf.fill f55=[sp]
mov f56=f0
;;
ldf.fill f57=[sp]
ldf.fill f58=[sp]
mov f59=f0
;;
ldf.fill f60=[sp]
ldf.fill f61=[sp]
mov f62=f0
;;
ldf.fill f63=[sp]
ldf.fill f64=[sp]
mov f65=f0
;;
ldf.fill f66=[sp]
ldf.fill f67=[sp]
mov f68=f0
;;
ldf.fill f69=[sp]
ldf.fill f70=[sp]
mov f71=f0
;;
ldf.fill f72=[sp]
ldf.fill f73=[sp]
mov f74=f0
;;
ldf.fill f75=[sp]
ldf.fill f76=[sp]
mov f77=f0
;;
ldf.fill f78=[sp]
ldf.fill f79=[sp]
mov f80=f0
;;
ldf.fill f81=[sp]
ldf.fill f82=[sp]
mov f83=f0
;;
ldf.fill f84=[sp]
ldf.fill f85=[sp]
mov f86=f0
;;
ldf.fill f87=[sp]
ldf.fill f88=[sp]
mov f89=f0
;;
ldf.fill f90=[sp]
ldf.fill f91=[sp]
mov f92=f0
;;
ldf.fill f93=[sp]
ldf.fill f94=[sp]
mov f95=f0
;;
ldf.fill f96=[sp]
ldf.fill f97=[sp]
mov f98=f0
;;
ldf.fill f99=[sp]
ldf.fill f100=[sp]
mov f101=f0
;;
ldf.fill f102=[sp]
ldf.fill f103=[sp]
mov f104=f0
;;
ldf.fill f105=[sp]
ldf.fill f106=[sp]
mov f107=f0
;;
ldf.fill f108=[sp]
ldf.fill f109=[sp]
mov f110=f0
;;
ldf.fill f111=[sp]
ldf.fill f112=[sp]
mov f113=f0
;;
ldf.fill f114=[sp]
ldf.fill f115=[sp]
mov f116=f0
;;
ldf.fill f117=[sp]
ldf.fill f118=[sp]
mov f119=f0
;;
ldf.fill f120=[sp]
ldf.fill f121=[sp]
mov f122=f0
;;
ldf.fill f123=[sp]
ldf.fill f124=[sp]
mov f125=f0
;;
ldf.fill f126=[sp]
mov f127=f0
br.ret.sptk.few rp
END(__ia64_init_fpu)
/*
* Switch execution mode from virtual to physical or vice versa.
*
* Inputs:
* r16 = new psr to establish
*
* Note: RSE must already be in enforced lazy mode
*/
GLOBAL_ENTRY(ia64_switch_mode)
{
alloc r2=ar.pfs,0,0,0,0
rsm psr.i | psr.ic // disable interrupts and interrupt collection
mov r15=ip
}
;;
{
flushrs // must be first insn in group
srlz.i
shr.u r19=r15,61 // r19 <- top 3 bits of current IP
}
;;
mov cr.ipsr=r16 // set new PSR
add r3=1f-ia64_switch_mode,r15
xor r15=0x7,r19 // flip the region bits
mov r17=ar.bsp
mov r14=rp // get return address into a general register
// switch RSE backing store:
;;
dep r17=r15,r17,61,3 // make ar.bsp physical or virtual
mov r18=ar.rnat // save ar.rnat
;;
mov ar.bspstore=r17 // this steps on ar.rnat
dep r3=r15,r3,61,3 // make rfi return address physical or virtual
;;
mov cr.iip=r3
mov cr.ifs=r0
dep sp=r15,sp,61,3 // make stack pointer physical or virtual
;;
mov ar.rnat=r18 // restore ar.rnat
dep r14=r15,r14,61,3 // make function return address physical or virtual
rfi // must be last insn in group
;;
1: mov rp=r14
br.ret.sptk.few rp
END(ia64_switch_mode)
#ifdef CONFIG_IA64_BRL_EMU
/*
* Assembly routines used by brl_emu.c to set preserved register state.
*/
#define SET_REG(reg) \
GLOBAL_ENTRY(ia64_set_##reg); \
alloc r16=ar.pfs,1,0,0,0; \
mov reg=r32; \
;; \
br.ret.sptk rp; \
END(ia64_set_##reg)
SET_REG(b1);
SET_REG(b2);
SET_REG(b3);
SET_REG(b4);
SET_REG(b5);
#endif /* CONFIG_IA64_BRL_EMU */
|